公开(公告)号：US08941628B2

公开(公告)日：2015-01-27

申请号：US13392952

申请日：2010-05-24

申请人： Yoshimitsu Yamauchi

发明人： Yoshimitsu Yamauchi

IPC分类号： G09G5/00 ,  G09G3/36 ,  G02F1/1362

CPC分类号： G09G3/3659 ,  G02F1/13624 ,  G09G2300/0852

摘要： A display device includes liquid crystal capacitor element formed between a pixel electrode and a counter electrode. One terminals of the pixel electrode, a first switch circuit, and a second switch circuit, and a first terminal of a second transistor form an internal node. The first switch circuit and the second switch circuit have other terminals connected to a source line. The second switch circuit is configured by a series circuit of transistors, and a control terminal of the transistor, a second terminal of the transistor, and one terminal of a boost capacitor element form an output node. The other terminal of the boost capacitor element is connected to a boost line, the control terminal of the transistor is connected to a reference line, and the control terminal of the transistor is connected to a selecting line.

摘要翻译： 显示装置包括形成在像素电极和对电极之间的液晶电容元件。 像素电极的一个端子，第一开关电路和第二开关电路以及第二晶体管的第一端子形成内部节点。 第一开关电路和第二开关电路具有连接到源极线的其它端子。 第二开关电路由晶体管的串联电路构成，晶体管的控制端子，晶体管的第二端子和升压电容器元件的一个端子构成输出节点。 升压电容元件的另一个端子连接到升压线，晶体管的控制端连接到参考线，并且晶体管的控制端连接到选择线。

公开(公告)号：US08847866B2

公开(公告)日：2014-09-30

申请号：US13376389

申请日：2010-06-07

申请人： Yoshimitsu Yamauchi

发明人： Yoshimitsu Yamauchi

IPC分类号： G09G3/36

CPC分类号： G09G3/3648 ,  G09G2300/0814 ,  G09G2300/0876 ,  G09G2330/021

摘要： A liquid crystal display device is provided which is capable of sufficiently decreasing power consumption in permanent display of still images while keeping high quality display in transparent mode, in high resolution display panels. In each pixel circuit, a pixel electrode is connected to a source line via a third transistor. When a refreshing circuit performs a refreshing operation, a boosting signal line is supplied with a voltage pulse. If the pixel electrode is at a high voltage level at this time point, a voltage at a node is boosted and a first transistor turns ON to supply a reference voltage to the pixel electrode as a refreshing voltage. If the pixel electrode is at a low voltage level, there is no boost, and the first transistor stays in OFF state, so a node assumes a voltage which is given by an off-resistance ratio of the first and the third transistors, and this voltage is supplied to the pixel electrode.

摘要翻译： 提供了一种液晶显示装置，其能够在高分辨率显示面板中以透明模式保持高质量显示的同时，充分降低静止图像的永久显示中的功耗。 在每个像素电路中，像素电极经由第三晶体管连接到源极线。 当刷新电路进行刷新操作时，向升压信号线提供电压脉冲。 如果在该时间点像素电极处于高电压电平，则节点处的电压被提升，并且第一晶体管导通以向像素电极提供参考电压作为刷新电压。 如果像素电极处于低电压电平，则不存在升压，并且第一晶体管保持截止状态，因此节点呈现由第一和第三晶体管的截止电阻比给出的电压，并且这个 电压被提供给像素电极。

公开(公告)号：US08704809B2

公开(公告)日：2014-04-22

申请号：US13375614

申请日：2010-06-07

申请人： Yoshimitsu Yamauchi

发明人： Yoshimitsu Yamauchi

IPC分类号： G06F3/038 ,  G09G5/00

CPC分类号： G09G3/3659 ,  G09G3/3258 ,  G09G2300/0866 ,  G09G2300/0876 ,  G09G2330/021

摘要： An embodiment of the present invention provides a liquid crystal display device. In each pixel circuit, a pixel electrode is connected to a source line via a third transistor. When a refreshing circuit performs a refreshing operation, a boosting signal line is supplied with a voltage pulse. If the pixel electrode is at a high voltage level at this time point, a voltage at a node is boosted and a first transistor turns ON to supply a refreshing voltage to the pixel electrode. If the pixel electrode is at a low voltage level, there is no boost, and the first transistor stays in OFF state, so a node assumes a voltage which is given by an off-resistance ratio of the first and the third transistors, and this voltage is supplied to the pixel electrode.

摘要翻译： 本发明的实施例提供一种液晶显示装置。 在每个像素电路中，像素电极经由第三晶体管连接到源极线。 当刷新电路进行刷新操作时，向升压信号线提供电压脉冲。 如果在该时间点像素电极处于高电压电平，则节点处的电压被升高，并且第一晶体管导通以向像素电极提供刷新电压。 如果像素电极处于低电压电平，则不存在升压，并且第一晶体管保持截止状态，因此节点呈现由第一和第三晶体管的截止电阻比给出的电压，并且这个 电压被提供给像素电极。

公开(公告)号：US08610197B2

公开(公告)日：2013-12-17

申请号：US13201584

申请日：2009-12-14

申请人： Naoki Ueda ,  Yoshimitsu Yamauchi

发明人： Naoki Ueda ,  Yoshimitsu Yamauchi

IPC分类号： H01L29/786 ,  H01L29/788

CPC分类号： H01L27/11524 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

摘要： Provided is a nonvolatile memory 10 having a selective gate SG formed below a silicon layer 14, which is to be a channel region formed between a source region S and a drain region D of a transistor, through a gate insulating film 15 between the silicon layer and the selective gate, a floating gate FG formed on a part over the silicon layer 14 through a gate insulating film 16, and a control gate CG connected to the floating gate FG. The selective gate SG has one end overlapping the source region S through the gate insulating film 15, and the floating gate FG has one end overlapping the drain region D through the gate insulating film 16, and the other end separated from the source region S and overlapping the silicon layer 14 through the gate insulating film 16. Thus, a nonvolatile memory whose performance is not deteriorated even when it is formed on an insulating substrate having a low heat dissipating characteristic can be achieved.

摘要翻译： 提供了一种非易失性存储器10，其具有形成在作为在晶体管的源极区域S和漏极区域D之间形成的沟道区域的硅层14下方的选择栅极SG，通过硅层之间的栅极绝缘膜15 选择栅极，通过栅极绝缘膜16形成在硅层14上的部分上的浮置栅极FG，以及连接到浮置栅极FG的控制栅极CG。 选择栅极SG的一端通过栅极绝缘膜15与源极区域S重叠，并且浮置栅极FG的一端通过栅极绝缘膜16与漏极区域D重叠，另一端与源极区域S分离， 通过栅极绝缘膜16与硅层14重叠。因此，即使在具有低散热特性的绝缘基板上形成性能也不会劣化的非易失性存储器。

公开(公告)号：US20130106824A1

公开(公告)日：2013-05-02

申请号：US13809942

申请日：2011-05-16

申请人： Yoshimitsu Yamauchi

发明人： Yoshimitsu Yamauchi

IPC分类号： G09G5/00

CPC分类号： G09G5/00 ,  G09G3/3258 ,  G09G3/3291 ,  G09G3/3614 ,  G09G3/3655 ,  G09G3/3688 ,  G09G2300/0426 ,  G09G2320/0209 ,  G09G2320/0238

摘要： A liquid crystal display device includes a data signal line driving circuit which separately drives data signal lines of an active matrix pixel array. One vertical period is divided into a scanning period and a non-scanning period. The data signal line driving circuit applies a signal voltage corresponding to the pixel data having the same polarity to the same data signal line with a predetermined fixed potential as a reference regardless of an order of a selected scanning signal line in the scanning period, and applies an intermediate voltage between maximum and minimum values of pixel voltages to each data signal line in the non-scanning period, the pixel voltages being respectively held in the pixel electrodes of the pixels connected to each data signal line.

摘要翻译： 液晶显示装置包括分别驱动有源矩阵像素阵列的数据信号线的数据信号线驱动电路。 一个垂直周期被分为扫描周期和非扫描周期。 数据信号线驱动电路将与具有相同极性的像素数据相对应的信号电压以与预定固定电位相同的数据信号线作为基准进行施加，而与扫描期间内所选择的扫描信号线的顺序无关，并且应用 在非扫描周期中，每个数据信号线的像素电压的最大值和最小值之间的中间电压，像素电压分别保持在连接到每个数据信号线的像素的像素电极中。

公开(公告)号：US20120299899A1

公开(公告)日：2012-11-29

申请号：US13522618

申请日：2010-11-19

申请人： Yoshimitsu Yamauchi

发明人： Yoshimitsu Yamauchi

IPC分类号： G09G5/00

CPC分类号： G09G3/3648 ,  G09G3/36 ,  G09G3/3614 ,  G09G3/3618 ,  G09G3/3655 ,  G09G3/3659 ,  G09G2300/043 ,  G09G2300/0465 ,  G09G2300/0814 ,  G09G2300/0819 ,  G09G2300/0852 ,  G09G2300/0876 ,  G09G2310/08 ,  G09G2320/0247 ,  G09G2320/043 ,  G09G2330/021

摘要： A display device which can prevent deterioration of a liquid crystal and reduction in display quality at low power consumption without lowering an aperture ratio is provided. An opposite voltage (Vcom) is applied to an opposite electrode (80) of a liquid crystal capacitive element (Clc). One ends of a pixel electrode (20), a first switch circuit (22), a second switch circuit (23), and a first terminal of a second transistor (T2) form an internal node (N1). The other ends of the first switch circuit (22) and the second switch circuit (23) are connected to a source line (SL) and a voltage supply line (VSL), respectively. A control terminal of a first transistor (T1) in the second switch circuit (23), a second terminal of the second transistor (T2), and one end of a boost capacitive element (Cbst) form an output node (N2). The other end of the boost capacitive element (Cbst) and the control terminal of the second transistor (T2) are connected to a boost line (BST) and a reference line (REF), respectively. This configuration makes it possible to perform an action (self-refresh action) to return the absolute value of the voltage between both ends of a display element part to the value at the time of a last writing action without performing a writing action.

摘要翻译： 提供一种能够防止液晶劣化并且在低功耗下降低显示质量而不降低开口率的显示装置。 将相对电压（Vcom）施加到液晶电容元件（Clc）的相对电极（80）。 像素电极（20），第一开关电路（22），第二开关电路（23）和第二晶体管（T2）的第一端子的一端形成内部节点（N1）。 第一开关电路（22）和第二开关电路（23）的另一端分别连接到源极线（SL）和电压供给线（VSL）。 第二开关电路（23）中的第一晶体管（T1）的控制端子，第二晶体管（T2）的第二端子和升压电容元件（Cbst）的一端形成输出节点（N2）。 升压电容元件（Cbst）的另一端和第二晶体管（T2）的控制端分别连接到升压线（BST）和基准线（REF）。 该配置使得可以执行动作（自刷新动作），以将显示元件部分的两端之间的电压的绝对值返回到上一次写入动作时的值而不执行写入动作。

公开(公告)号：US20120218252A1

公开(公告)日：2012-08-30

申请号：US13508003

申请日：2010-07-22

申请人： Yoshimitsu Yamauchi

发明人： Yoshimitsu Yamauchi

IPC分类号： G06F3/038

CPC分类号： G09G3/36 ,  G09G3/3233 ,  G09G3/3614 ,  G09G3/3618 ,  G09G3/3648 ,  G09G3/3655 ,  G09G3/3659 ,  G09G2300/0465 ,  G09G2300/0814 ,  G09G2300/0819 ,  G09G2300/0852 ,  G09G2300/0876 ,  G09G2310/08 ,  G09G2320/0247 ,  G09G2330/021

摘要： A display device in which a pixel voltage is held at low power consumption without any influence from fluctuation in threshold voltage is provided. A liquid crystal capacitor element (Clc) is formed between a pixel electrode (20) and a counter electrode (80). A counter voltage (Vcom) is applied to the counter electrode (80). The pixel electrode (20), one ends of a first switch circuit (22) and a second switch circuit (23), and a first terminal of a second transistor (T2) form an internal node (N1). The other end of the first switch circuit (22) is connected to a source line (SL). The second switch circuit (23) has the other end connected to a voltage supply line (VSL) and is a series circuit of transistors (T1 and T2). A control terminal of the transistor (T1), a second terminal of the transistor (T2), and one end of the boost capacitor element (Cbst) form an output node (N2). The other end of the boost capacitor element (Cbst), the control terminal of the transistor (T2), and the control terminal of the transistor (T3) are connected to a boost line (BST), a reference line (REF), and a selecting line (SEL), respectively.

摘要翻译： 提供了其中像素电压保持在低功耗而不受阈值电压波动影响的显示装置。 在像素电极（20）和对置电极（80）之间形成液晶电容元件（Clc）。 向对电极（80）施加反电压（Vcom）。 像素电极（20），第一开关电路（22）和第二开关电路（23）的一端以及第二晶体管（T2）的第一端子形成内部节点（N1）。 第一开关电路（22）的另一端连接到源极线（SL）。 第二开关电路（23）的另一端与电压供给线（VSL）连接，是晶体管（T1，T2）的串联电路。 晶体管（T1）的控制端子，晶体管（T2）的第二端子以及升压电容器元件（Cbst）的一端形成输出节点（N2）。 升压电容器元件（Cbst）的另一端，晶体管（T2）的控制端子和晶体管（T3）的控制端子连接到升压线（BST），参考线（REF）和 选择线（SEL）。

公开(公告)号：US07276761B2

公开(公告)日：2007-10-02

申请号：US11086565

申请日：2005-03-23

申请人： Yoshimitsu Yamauchi

发明人： Yoshimitsu Yamauchi

IPC分类号： H01L29/792

CPC分类号： H01L27/112 ,  H01L27/11253

摘要： A semiconductor memory device of the invention comprises a plurality of bit lines formed by implanting a second conductive-type impurity in a first conductive-type semiconductor substrate; a thick insulating film on the bit lines; a thin insulating film between the neighboring bit lines; and a plurality of word lines formed on the thick and thin insulating films so as to cross the bit lines, wherein each of the word lines includes a plurality of first conductors and a second conductor which electrically connects the first conductors in series, the respective first conductors are formed on the thin insulating film, the top face of the thickest portion of the thick insulating film is higher than the top face of the first conductors, and the film thickness of the thick insulating film is made thinner toward the end.

摘要翻译： 本发明的半导体存储器件包括通过在第一导电型半导体衬底中注入第二导电型杂质形成的多个位线; 位线上的厚绝缘膜; 相邻位线之间的薄绝缘膜; 以及形成在厚而薄的绝缘膜上以跨越位线的多个字线，其中每个字线包括多个第一导体和将第一导体串联电连接的第二导体，第一 导体形成在薄绝缘膜上，厚绝缘膜的最厚部分的顶面高于第一导体的顶面，并且使厚绝缘膜的膜厚朝向端部变薄。

公开(公告)号：US07187029B2

公开(公告)日：2007-03-06

申请号：US10230369

申请日：2002-08-29

申请人： Yasuhiro Sugita ,  Yoshimitsu Yamauchi

发明人： Yasuhiro Sugita ,  Yoshimitsu Yamauchi

IPC分类号： H01L29/788

CPC分类号： H01L27/11519 ,  G11C16/0491 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/7883

摘要： A nonvolatile semiconductor memory device has a cell which includes a drain diffusion region and a source diffusion region formed on a surface layer of a semiconductor substrate; a first insulating film formed between the source diffusion region and the drain diffusion region; a floating gate formed on the first insulating film; a second insulating film formed on the floating gate; a first control gate formed on the second insulating film; a third insulating film formed on the first control gate and a sidewall thereof and on a sidewall of the floating gate; and a second control gate formed on the first control gate with the third insulating film interposed therebetween.

摘要翻译： 非易失性半导体存储器件具有包括漏极扩散区域和形成在半导体衬底的表面层上的源极扩散区域的单元; 形成在所述源极扩散区域和所述漏极扩散区域之间的第一绝缘膜; 形成在第一绝缘膜上的浮栅; 形成在浮动栅极上的第二绝缘膜; 形成在所述第二绝缘膜上的第一控制栅极; 第三绝缘膜，形成在所述第一控制栅极及其侧壁上以及所述浮动栅极的侧壁上; 以及形成在第一控制栅极上的第二控制栅极，其间插入有第三绝缘膜。

公开(公告)号：US20050212023A1

公开(公告)日：2005-09-29

申请号：US11086565

申请日：2005-03-23

申请人： Yoshimitsu Yamauchi

发明人： Yoshimitsu Yamauchi

IPC分类号： H01L21/8247 ,  H01L21/8239 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/108 ,  H01L27/112 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/112 ,  H01L27/11253

摘要： A semiconductor memory device of the invention comprises a plurality of bit lines formed by implanting a second conductive-type impurity in a first conductive-type semiconductor substrate; a thick insulating film on the bit lines; a thin insulating film between the neighboring bit lines; and a plurality of word lines formed on the thick and thin insulating films so as to cross the bit lines, wherein each of the word lines includes a plurality of first conductors and a second conductor which electrically connects the first conductors in series, the respective first conductors are formed on the thin insulating film, the top face of the thickest portion of the thick insulating film is higher than the top face of the first conductors, and the film thickness of the thick insulating film is made thinner toward the end.

摘要翻译： 本发明的半导体存储器件包括通过在第一导电型半导体衬底中注入第二导电型杂质形成的多个位线; 位线上的厚绝缘膜; 相邻位线之间的薄绝缘膜; 以及形成在厚而薄的绝缘膜上以跨越位线的多个字线，其中每个字线包括多个第一导体和将第一导体串联电连接的第二导体，第一 导体形成在薄绝缘膜上，厚绝缘膜的最厚部分的顶面高于第一导体的顶面，并且使厚绝缘膜的膜厚朝向端部变薄。