公开(公告)号：US08660189B2

公开(公告)日：2014-02-25

申请号：US12817344

申请日：2010-06-17

申请人： Tadamasa Toma ,  Shinya Kadono ,  Masayasu Iguchi ,  Tomoyuki Okada ,  Yoshinori Matsui ,  Satoshi Kondo ,  Hiroshi Yahata ,  Wataru Ikeda

发明人： Tadamasa Toma ,  Shinya Kadono ,  Masayasu Iguchi ,  Tomoyuki Okada ,  Yoshinori Matsui ,  Satoshi Kondo ,  Hiroshi Yahata ,  Wataru Ikeda

IPC分类号： H04N11/02

CPC分类号： H04N9/8042 ,  G11B27/3027 ,  G11B27/329 ,  G11B2220/2541 ,  H04N5/85 ,  H04N9/8063 ,  H04N9/8205 ,  H04N9/8227 ,  H04N19/13 ,  H04N19/179 ,  H04N19/61

摘要： A moving image encoding method of encoding a moving image while switching between variable-length encoding schemes. In this method, a continuous unit to be continuously reproduced is determined (S5201), a stream is generated by encoding the moving image without switching between variable-length encoding schemes in the continuous unit (S5202), and management information is generated that includes a first flag information indicating that a variable-length encoding scheme is fixed in the continuous unit (S5204, and S5205).

摘要翻译： 一种在可变长度编码方案之间切换的同时对运动图像进行编码的运动图像编码方法。 在该方法中，确定要连续重放的连续单元（S5201），通过对运动图像进行编码而不在连续单元中的可变长度编码方案之间进行切换来生成流（S5202），生成包括 指示可变长度编码方案在连续单元中固定的第一标志信息（S5204和S5205）。

公开(公告)号：US20120262974A1

公开(公告)日：2012-10-18

申请号：US13536280

申请日：2012-06-28

申请人： Yoshinori MATSUI ,  Toshio SUGANO ,  Hiroaki IKEDA

发明人： Yoshinori MATSUI ,  Toshio SUGANO ,  Hiroaki IKEDA

IPC分类号： G11C5/02

CPC分类号： G11C11/408 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C7/1051 ,  G11C7/1063 ,  G11C8/12 ,  G11C29/1201 ,  G11C29/26 ,  G11C29/48 ,  H01L23/5384 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2224/0401

摘要： In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip.

摘要翻译： 在包括以预定数据宽度和传送速率发送/接收系统数据信号的多个DRAM芯片的存储器模块中，并且发送/接收具有较大数据宽度和较低传送速率的内部数据信号与 系统数据信号，系统数据信号的传输速率受到限制。 构成存储器模块的DRAM的电流消耗大，阻碍速度增加。 对于该存储模块，多个DRAM芯片堆叠在IO芯片上。 每个DRAM芯片通过贯通电极连接到IO芯片，并且包括用于通过IO芯片相互转换每个DRAM芯片中的系统数据信号和内部数据信号的结构。 因此，可以缩短DRAM芯片之间的布线，并且可以仅在IO芯片上设置具有大电流消耗的DLL。

公开(公告)号：US08271740B2

公开(公告)日：2012-09-18

申请号：US12411974

申请日：2009-03-26

申请人： Seiji Miura ,  Yoshinori Matsui ,  Kazuhiko Abe ,  Shoji Kaneko

发明人： Seiji Miura ,  Yoshinori Matsui ,  Kazuhiko Abe ,  Shoji Kaneko

IPC分类号： G06F12/00

CPC分类号： G11C7/1075 ,  G06F13/1663

摘要： In an information processing system, a plurality of information processing devices CHIP0 and CHIP1 are connected to multiport memory MPMEM0 that has a plurality of ports, and memory areas in multiport memory MPMEM0 can be altered to memory areas occupied by particular ports and memory areas shared by a plurality of ports. At such times, immediately after the occurrence of a request from a port, the status of this request may be supplied from other ports.

摘要翻译： 在信息处理系统中，多个信息处理装置CHIP0和CHIP1连接到具有多个端口的多端口存储器MPMEM0，并且多端口存储器MPMEM0中的存储区域可以被改变为由特定端口和存储区域所占用的存储区域 多个端口。 在这样的时刻，在从端口发出请求之后，可以从其他端口提供该请求的状态。

公开(公告)号：US20120038406A1

公开(公告)日：2012-02-16

申请号：US13208976

申请日：2011-08-12

申请人： Yoshinori MATSUI

发明人： Yoshinori MATSUI

IPC分类号： H03K5/06

CPC分类号： H03K5/04 ,  G11C7/04 ,  G11C7/1039 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1093 ,  G11C7/1096 ,  G11C7/222 ,  H03K5/133 ,  H03K5/153

摘要： To cancel a delay time that occurs in a delay circuit due to temperature and voltage changes. The delay circuit includes a plurality of first and second inverters that are each composed of an N-channel first transistor and a P-channel second transistor connected in series, and P-channel third transistors that are connected between a first power supply wiring and the input nodes of the second inverters. According to the present invention, the presence of the third transistors cancels characteristic variations of the second transistors included in the respective plurality of inverters even if there are changes in temperature, voltage, etc. Consequently, when temperature, voltage, or the like changes, variations in the amount of delay of the entire delay circuit can be regarded as resulting from characteristic variations of the first transistors.

摘要翻译： 取消由于温度和电压变化引起的延迟电路中的延迟时间。 延迟电路包括多个第一和第二反相器，它们分别由串联连接的N沟道第一晶体管和P沟道第二晶体管构成，P沟道第三晶体管连接在第一电源布线和第 第二个逆变器的输入节点。 根据本发明，即使存在温度，电压等变化，第三晶体管的存在也抵消了包括在多个逆变器中的第二晶体管的特性变化。因此，当温度，电压等发生变化时， 整个延迟电路的延迟量的变化可以被认为是由第一晶体管的特性变化引起的。

公开(公告)号：US08078581B2

公开(公告)日：2011-12-13

申请号：US12029139

申请日：2008-02-11

申请人： Kensuke Amaki ,  Kenichi Oyamada ,  Takeyuki Imazu ,  Yoshinori Matsui

发明人： Kensuke Amaki ,  Kenichi Oyamada ,  Takeyuki Imazu ,  Yoshinori Matsui

IPC分类号： G06F7/00

CPC分类号： G06F11/2074 ,  G06F11/2064 ,  G06F11/2082 ,  G06F2201/855

摘要： A plurality of second groups respectively including one or more second volumes are configured in correspondence with each of the first groups of a remote copy source in a remote copy destination, journals are acquired from the first storage apparatus periodically and in the order the journals were created for each of the configured second groups, and the acquired journals are reflected in the corresponding second volume in the corresponding second group. In addition, the latest time stamp of each of the second groups containing the journals retained in the second volume in an unreflected state is compared, the time difference of the latest and oldest time stamps is detected, and prescribed control processing is executed for acquiring the journals regarding the second group with the oldest time stamp in preference to the journals regarding other second groups when the time difference exceeds a preset threshold value.

摘要翻译： 分别包括一个或多个第二卷的多个第二组被配置为与远程复制目的地中的远程复制源的第一组中的每一个相对应，周期性地从第一存储装置获取期刊，并且按照创建的期刊的顺序 对于每个配置的第二组，并且所获取的日志被反映在相应的第二组中的对应的第二卷中。 另外，比较包含保持在未反射状态的第二卷中的期刊的每个第二组的最新时间戳，检测最新和最旧的时间戳的时间差，并且执行规定的控制处理以获取 当时间差超过预设阈值时，关于具有最早时间戳的第二组的期刊优先于关于其他第二组的期刊。

公开(公告)号：US08072492B2

公开(公告)日：2011-12-06

申请号：US10594147

申请日：2005-05-17

申请人： Satoshi Kondo ,  Hisao Sasai ,  Takahiro Nishi ,  Tadamasa Toma ,  Toshiyasu Sugio ,  Yoshinori Matsui

发明人： Satoshi Kondo ,  Hisao Sasai ,  Takahiro Nishi ,  Tadamasa Toma ,  Toshiyasu Sugio ,  Yoshinori Matsui

IPC分类号： H04N7/18 ,  H04M1/00

CPC分类号： H04N5/76 ,  H04N5/445 ,  H04N21/4122 ,  H04N21/41407 ,  H04N21/4227 ,  H04N21/4316 ,  H04N21/4333 ,  H04N21/44008 ,  H04N21/478 ,  H04N21/4786 ,  H04N21/4882 ,  H04N21/812

摘要： To provide a mobile terminal device which can perform an operation reflecting the intention of a user when an event, such as the arrival of an incoming phone call or an email, occurs while a television broadcast is being displayed, and which can also improve the operability. A mobile terminal device is composed of: a TV reception unit which receives a television broadcast signal; an output control unit which controls outputs of video and audio of the television broadcast, auxiliary information of the television broadcast, the email, audio of the phone call, and video and audio of a video phone call, to a first display unit, a second display unit, and an audio reproduction unit; a recording control unit which records a television broadcast program onto a recording medium; a reproduction control unit which reproduces the television broadcast program recorded on the recording medium; a control unit which controls an operation performed when the email or the phone call is receives while the television broadcast is being displayed; and an unfold/fold detection unit which detects whether the mobile terminal device is folded or unfolded.

摘要翻译： 为了提供一种移动终端设备，当在显示电视广播的同时，当诸如到来的电话呼叫或电子邮件等事件发生时，可以执行反映用户意图的操作，并且还可以提高可操作性 。 一种移动终端设备包括：接收电视广播信号的电视接收单元; 输出控制单元，其将电视广播的视频和音频输出，电视广播的辅助信息，电话，电话的音频以及视频电话的视频和音频的输出控制到第一显示单元，第二显示单元 显示单元和音频再现单元; 记录控制单元，其将电视广播节目记录到记录介质上; 再现控制单元，其再现记录在记录介质上的电视广播节目; 控制单元，其控制在显示电视广播时接收到电子邮件或电话呼叫时执行的操作; 以及展开/折叠检测单元，其检测移动终端设备是否被折叠或展开。

公开(公告)号：US20110261640A1

公开(公告)日：2011-10-27

申请号：US13067849

申请日：2011-06-29

申请人： Yoshinori Matsui

发明人： Yoshinori Matsui

IPC分类号： G11C8/16 ,  G11C8/10

CPC分类号： G11C7/1075

摘要： A semiconductor device, includes a first memory cell array, a second memory cell array, a command decoder configured to produce a transfer command to transfer a data stored in a first area of the first memory cell array to a second area of the second memory cell array, when receiving a read command to the first memory cell array and sequentially a write command to the second cell memory array, a first address generator configured to produce a first internal address for designating the first area of the first memory cell array when receiving the transfer command from the command decoder; and a second address generator configured to produce a second internal address for designating the second area of the second memory cell array when receiving the transfer command from the command decoder.

摘要翻译： 一种半导体器件，包括第一存储单元阵列，第二存储单元阵列，命令解码器，被配置为产生将存储在第一存储单元阵列的第一区域中的数据传送到第二存储单元的第二区域的传送命令 阵列，当接收到第一存储单元阵列的读取命令并且顺序地向第二单元存储器阵列写入命令时，第一地址生成器被配置为产生用于指定第一存储单元阵列的第一区域的第一内部地址， 命令解码器传输命令; 以及第二地址发生器，被配置为当从命令解码器接收到传送命令时，产生用于指定第二存储单元阵列的第二区域的第二内部地址。

公开(公告)号：US07978557B2

公开(公告)日：2011-07-12

申请号：US12318731

申请日：2009-01-07

申请人： Yoshinori Matsui

发明人： Yoshinori Matsui

IPC分类号： G11C7/00

CPC分类号： G11C7/1075

摘要： A semiconductor device that includes a plurality of memory cell arrays, a plurality of ports, a plurality of internal address generating circuits, and a controller. The plurality of internal address generating circuits may generate first and second internal addresses of first and second memory cell arrays of the plurality of memory cell arrays. The first internal address may designate a first area of the first memory cell array. The second internal address may designate a second area of the second memory cell array. The controller reads a series of data from the first area sequentially and writes the series of read data into the second area sequentially without transferring the series of read data to the plurality of ports.

摘要翻译： 一种半导体器件，包括多个存储单元阵列，多个端口，多个内部地址生成电路和控制器。 多个内部地址产生电路可以生成多个存储单元阵列中的第一和第二存储单元阵列的第一和第二内部地址。 第一内部地址可以指定第一存储单元阵列的第一区域。 第二内部地址可以指定第二存储单元阵列的第二区域。 控制器顺序地从第一区域读取一系列数据，并将读取数据序列顺序地写入第二区域，而不将该系列读取数据传送到多个端口。

公开(公告)号：US20090228283A1

公开(公告)日：2009-09-10

申请号：US11578781

申请日：2006-02-24

申请人： Tadamasa Toma ,  Yoshinori Matsui ,  Shinya Kadono

发明人： Tadamasa Toma ,  Yoshinori Matsui ,  Shinya Kadono

IPC分类号： G10L21/00

CPC分类号： G10L21/038

摘要： A data reproduction device is provided that can achieve seamless reproduction of a stream even at the switching positions of the validity of the bandwidth extension function even in the case where the validity of the bandwidth extension function is switched in the stream. A data reproduction device (2000) includes: an input frequency obtainment unit (2001) which analyzes header information Hdr and obtains an input frequency FSin which is the frequency of basic data; an output frequency determination unit (2002) which performs predetermined processing based on the input frequency FSin and determines an output frequency FSout which is the sampling frequency of a decoded frame Fdata; and a decoding unit (2003) which, if the SBR function is valid in a frame to be decoded, decodes sample data at the input frequency FSin and extends the bandwidth of the sampling frequency up to the output frequency FSout through the SBR processing on the decoding result, while if the SBR function is not valid in the frame, upsamples the decoding result obtained at the input frequency FSin to the output frequency FSout.

摘要翻译： 即使在带宽扩展功能的有效性在流中被切换的情况下，也可以实现即使在带宽扩展功能的有效性的切换位置，也能实现流的无缝再现。 数据再现装置（2000）包括：输入频率获取单元（2001），其分析标题信息Hdr并获得作为基本数据的频率的输入频率FSin; 输出频率确定单元（2002），其基于输入频率FSin执行预定处理，并确定作为解码帧Fdata的采样频率的输出频率FSout; 以及解码单元（2003），如果SBR功能在要解码的帧中有效，则以输入频率FSin解码采样数据，并且通过SBR处理将采样频率的带宽扩展到输出频率FSout 解码结果，而如果SBR功能在帧中无效，则将在输入频率FSin获得的解码结果上采样到输出频率FSout。

公开(公告)号：US20090219745A1

公开(公告)日：2009-09-03

申请号：US12435168

申请日：2009-05-04

申请人： Yoshinori Matsui ,  Toshio Sugano ,  Hiroaki Ikeda

发明人： Yoshinori Matsui ,  Toshio Sugano ,  Hiroaki Ikeda

IPC分类号： G11C5/02 ,  G11C5/06

CPC分类号： G11C11/408 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C7/1051 ,  G11C7/1063 ,  G11C8/12 ,  G11C29/1201 ,  G11C29/26 ,  G11C29/48 ,  H01L23/5384 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2224/0401

摘要： In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip.

摘要翻译： 在包括以预定数据宽度和传送速率发送/接收系统数据信号的多个DRAM芯片的存储器模块中，并且发送/接收具有较大数据宽度和较低传送速率的内部数据信号与 系统数据信号，系统数据信号的传输速率受到限制。 构成存储器模块的DRAM的电流消耗大，阻碍速度增加。 对于该存储器模块，多个DRAM芯片堆叠在IO芯片上。 每个DRAM芯片通过贯通电极连接到IO芯片，并且包括用于通过IO芯片相互转换每个DRAM芯片中的系统数据信号和内部数据信号的结构。 因此，可以缩短DRAM芯片之间的布线，并且可以仅在IO芯片上设置具有大电流消耗的DLL。