公开(公告)号：US07035154B2

公开(公告)日：2006-04-25

申请号：US10362891

申请日：2001-08-30

申请人： Hiroyuki Takahashi ,  Yoshiyuki Katou ,  Hideo Inaba ,  Shouzou Uchida ,  Masatoshi Sonoda

发明人： Hiroyuki Takahashi ,  Yoshiyuki Katou ,  Hideo Inaba ,  Shouzou Uchida ,  Masatoshi Sonoda

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/50016 ,  G11C11/401 ,  G11C29/12 ,  G11C29/46

摘要： The present invention provides a semiconductor memory device capable of checking operation in the worst case in address combinations, and its manufacturing method. Specific data for test are written into a memory cell array 30. Then, a test signal TE1 is set “1” to set a device in a test mode. Refresh addresses for test are then stored in a data store circuit 51. A first address for test is applied to an address terminal 21, whereby a normal read or write operation is accomplished based on the first address for test. A second address for test is applied to the address terminal 21, whereby a refresh operation is accomplished based on the address for test, and subsequently another normal read or write operation is accomplished based on the second address for test. Data of the memory cell array 30 are checked to decide the presence or absence of any abnormality.

摘要翻译： 本发明提供一种能够在地址组合中的最坏情况下检查操作的半导体存储器件及其制造方法。 用于测试的具体数据被写入存储单元阵列30.然后，将测试信号TE 1设置为“1”以将设备设置在测试模式中。 然后将用于测试的刷新地址存储在数据存储电路51中。用于测试的第一地址被应用于地址终端21，由此基于用于测试的第一地址来完成正常的读取或写入操作。 用于测试的第二地址被应用于地址终端21，由此基于用于测试的地址来完成刷新操作，并且随后基于第二测试地址来完成另一个正常的读取或写入操作。 对存储单元阵列30的数据进行检查，判定有无异常。

公开(公告)号：US06944081B2

公开(公告)日：2005-09-13

申请号：US10363298

申请日：2001-08-30

申请人： Hiroyuki Takahashi ,  Atsushi Nakagawa ,  Yoshiyuki Katou ,  Hideo Inaba ,  Noriaki Komatsu ,  Takuya Hirota ,  Masahiro Yoshida

发明人： Hiroyuki Takahashi ,  Atsushi Nakagawa ,  Yoshiyuki Katou ,  Hideo Inaba ,  Noriaki Komatsu ,  Takuya Hirota ,  Masahiro Yoshida

IPC分类号： G11C11/406 ,  G11C7/00

CPC分类号： G11C11/406

摘要： A semiconductor memory device capable of a further reduction in power consumption for refresh operation is provided. Cell arrays S0, S1 are divided into respective four blocks B0˜B3 and B10˜B13. In a normal read/write operation, by address data designating a word line, one of the cell arrays is selected, and also one block is selected in the selected cell array, and further one word line is selected in the selected block. In a refresh operation, one of the cell arrays is selected, and four blocks in the selected cell array are simultaneously refreshed. Namely, respective one word line is selected from each of the four blocks, and the selected word lines are refreshed, thereby to reduce a power comsumption as compared to when the plural cell arrays are refreshed.

摘要翻译： 提供能够进一步降低刷新操作的功耗的半导体存储器件。 单元阵列S 0，S 1被分成四个块B 0〜B 3和B 10〜B 13。 在通常的读/写操作中，通过指定字线的地址数据，选择单元阵列中的一个，并且在所选择的单元阵列中选择一个块，并且在所选块中还选择一个字线。 在刷新操作中，选择单元阵列之一，同时刷新所选单元阵列中的四个块。 也就是说，从四个块中的每一个中选择相应的一个字线，并且与多个单元阵列刷新时相比，刷新所选择的字线，从而降低功耗。