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公开(公告)号:US20080061407A1
公开(公告)日:2008-03-13
申请号:US11852079
申请日:2007-09-07
IPC分类号: H01L23/552 , H01L21/60
CPC分类号: H01L23/552 , H01L21/561 , H01L23/29 , H01L23/3121 , H01L23/3135 , H01L24/48 , H01L24/97 , H01L2224/48091 , H01L2224/48227 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01087 , H01L2924/07802 , H01L2924/15787 , H01L2924/16152 , H01L2924/181 , H01L2924/19105 , H01L2924/3011 , H01L2924/3025 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要: A semiconductor device package includes a semiconductor device mounted and electrically coupled to a substrate, a package body encapsulating the semiconductor device against a portion of an upper surface of the substrate; and an electromagnetic interference shielding layer formed over the package body and substantially enclosing the semiconductor device. The present invention further provides methods for manufacturing the semiconductor device package
摘要翻译: 半导体器件封装包括安装并电耦合到衬底的半导体器件,将半导体器件封装在衬底的上表面的一部分上的封装体; 以及形成在封装主体上并且基本上包围半导体器件的电磁干扰屏蔽层。 本发明还提供了制造半导体器件封装的方法
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公开(公告)号:US20080032452A1
公开(公告)日:2008-02-07
申请号:US11757795
申请日:2007-06-04
IPC分类号: H01L21/58
CPC分类号: H01L23/3114 , H01L24/11 , H01L24/13 , H01L2224/05001 , H01L2224/05026 , H01L2224/0557 , H01L2224/05571 , H01L2224/11 , H01L2224/11334 , H01L2224/13 , H01L2224/13099 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01087 , H01L2924/014 , H01L2924/07811 , H01L2924/14 , H01L2924/30107 , H01L2924/00 , H01L2224/05599 , H01L2224/05099
摘要: A chip scale package includes a patterned circuit layer attached to the active surface of a semiconductor chip through an anisotropic conductive adhesive layer such that contact pads on a lower surface of the patterned circuit layer are electrically coupled to corresponding bonding pads on the semiconductor chip. The patterned circuit layer has a plurality of openings formed therein at locations corresponding to the contact pads such that each of the contact pads has a portion exposed from an upper surface of the patterned circuit layer through the corresponding opening. A plurality of metal bumps are respectively disposed in the openings and mounted to the exposed portions of the contact pads for making external electrical connection. The present invention further provides a method for manufacturing the chip scale package at the wafer-level.
摘要翻译: 芯片级封装包括通过各向异性导电粘合剂层附着到半导体芯片的有源表面的图案化电路层,使得图案化电路层的下表面上的接触焊盘电耦合到半导体芯片上的对应焊盘。 图案化电路层在对应于接触焊盘的位置处具有形成在其中的多个开口,使得每个接触焊盘具有通过相应的开口从图案化电路层的上表面露出的部分。 多个金属凸块分别设置在开口中并安装到接触垫的暴露部分以进行外部电连接。 本发明还提供了一种在晶片级制造芯片级封装的方法。
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公开(公告)号:US20080042301A1
公开(公告)日:2008-02-21
申请号:US11898006
申请日:2007-09-07
申请人: Jun Young Yang , You Joo , You Pil Jung
发明人: Jun Young Yang , You Joo , You Pil Jung
IPC分类号: H01L23/28
CPC分类号: H01L23/29 , H01L21/561 , H01L23/3121 , H01L23/3135 , H01L23/552 , H01L24/48 , H01L24/97 , H01L2224/48091 , H01L2224/48227 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01087 , H01L2924/07802 , H01L2924/15787 , H01L2924/16152 , H01L2924/181 , H01L2924/19105 , H01L2924/3011 , H01L2924/3025 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要: A semiconductor device package includes a semiconductor device mounted and electrically coupled to a substrate, a package body encapsulating the semiconductor device against a portion of an upper surface of the substrate; and an electromagnetic interference shielding layer formed over the package body and substantially enclosing the semiconductor device. The electromagnetic interference shielding layer is a plated metal layer in contact with the package body, and the plated metal layer is connected to a ground trace extending on the upper surface of the substrate.
摘要翻译: 半导体器件封装包括安装并电耦合到衬底的半导体器件,封装体,其将半导体器件封装在衬底的上表面的一部分上; 以及形成在封装主体上并且基本上包围半导体器件的电磁干扰屏蔽层。 电磁干扰屏蔽层是与封装体接触的电镀金属层,并且电镀金属层连接到在基板的上表面上延伸的接地迹线。
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公开(公告)号:US20060170096A1
公开(公告)日:2006-08-03
申请号:US11047617
申请日:2005-02-02
IPC分类号: H01L23/34
CPC分类号: H01L23/3114 , H01L24/11 , H01L24/13 , H01L2224/05001 , H01L2224/05026 , H01L2224/0557 , H01L2224/05571 , H01L2224/11 , H01L2224/11334 , H01L2224/13 , H01L2224/13099 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01087 , H01L2924/014 , H01L2924/07811 , H01L2924/14 , H01L2924/30107 , H01L2924/00 , H01L2224/05599 , H01L2224/05099
摘要: A chip scale package includes a patterned circuit layer attached to the active surface of a semiconductor chip through an anisotropic conductive adhesive layer such that contact pads on a lower surface of the patterned circuit layer are electrically coupled to corresponding bonding pads on the semiconductor chip. The patterned circuit layer has a plurality of openings formed therein at locations corresponding to the contact pads such that each of the contact pads has a portion exposed from an upper surface of the patterned circuit layer through the corresponding opening. A plurality of metal bumps are respectively disposed in the openings and mounted to the exposed portions of the contact pads for making external electrical connection. The present invention further provides a method for manufacturing the chip scale package at the wafer-level.
摘要翻译: 芯片级封装包括通过各向异性导电粘合剂层附着到半导体芯片的有源表面的图案化电路层,使得图案化电路层的下表面上的接触焊盘电耦合到半导体芯片上的对应焊盘。 图案化电路层在对应于接触焊盘的位置处具有形成在其中的多个开口,使得每个接触焊盘具有通过相应的开口从图案化电路层的上表面暴露的部分。 多个金属凸块分别设置在开口中并安装到接触垫的暴露部分以进行外部电连接。 本发明还提供了一种在晶片级制造芯片级封装的方法。
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公开(公告)号:US20060145361A1
公开(公告)日:2006-07-06
申请号:US11028670
申请日:2005-01-05
IPC分类号: H01L23/28
CPC分类号: H01L23/552 , H01L21/561 , H01L23/29 , H01L23/3121 , H01L23/3135 , H01L24/48 , H01L24/97 , H01L2224/48091 , H01L2224/48227 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01087 , H01L2924/07802 , H01L2924/15787 , H01L2924/16152 , H01L2924/181 , H01L2924/19105 , H01L2924/3011 , H01L2924/3025 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要: A semiconductor device package includes a semiconductor device mounted and electrically coupled to a substrate, a package body encapsulating the semiconductor device against a portion of an upper surface of the substrate; and an electromagnetic interference shielding layer formed over the package body and substantially enclosing the semiconductor device. The present invention further provides methods for manufacturing the semiconductor device package.
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