公开(公告)号：US07271639B2

公开(公告)日：2007-09-18

申请号：US11392359

申请日：2006-03-28

申请人： Youichi Satou ,  Hiroaki Suzuki

发明人： Youichi Satou ,  Hiroaki Suzuki

IPC分类号： H03L5/00

CPC分类号： H03K3/356165 ,  H03K3/356113

摘要： Differential signals are supplied to gates of first and second transistors. One end and a gate of a third transistor are connected to a signal output node. One end and a gate of a fourth transistor are connected to the other end of the second transistor. A fifth transistor is connected between a power source and the other end of the third transistor. A sixth transistor is connected between a power source and the other end of the fourth transistor. A seventh transistor is inserted between the power source and the signal output node. An eighth transistor is inserted between the power source and the common connection node of the second and fourth transistor, and a gate of the eighth transistor is connected to the gate of the sixth transistor.

摘要翻译： 差分信号被提供给第一和第二晶体管的栅极。 第三晶体管的一端和栅极连接到信号输出节点。 第四晶体管的一端和栅极连接到第二晶体管的另一端。 第五晶体管连接在电源和第三晶体管的另一端之间。 第六晶体管连接在电源和第四晶体管的另一端之间。 第七晶体管插在电源和信号输出节点之间。 第八晶体管被插入在第二和第四晶体管的电源和公共连接节点之间，第八晶体管的栅极连接到第六晶体管的栅极。

公开(公告)号：US06445002B1

公开(公告)日：2002-09-03

申请号：US09621452

申请日：2000-07-21

申请人： Takehiro Hashimoto ,  Yutaka Tanaka ,  Tetsuya Asami ,  Youichi Satou ,  Noriaki Okumiya

发明人： Takehiro Hashimoto ,  Yutaka Tanaka ,  Tetsuya Asami ,  Youichi Satou ,  Noriaki Okumiya

IPC分类号： H01L2358

CPC分类号： H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method for setting appropriate initial-failure screening conditions when mass-producing semiconductor devices of multiple types, devices of each type being manufactured in a small number, the step of subjecting products of every type to an acceleration test is excluded, and instead, the failure ratio on the market of semiconductor devices of each type is estimated using a testing semiconductor device. Specifically, {circle around (1)} first, all types of semiconductor devices to be developed and mass-produced are classified into several groups. {circle around (2)} A test semiconductor device is developed which has the same number of elements, the same gate area, the same multi-layer wiring length and the same number of contact holes as the average number of elements, the average gate area, the average wiring length and the average number of contact holes of the semiconductor devices included in one of the type groups, respectively. The testing semiconductor device has main features (design rules, MOSFET structure, wiring structure, etc.) common to the types included in its corresponding type group, and a failed portion thereof, if any, can be easily detected by an analysis using a tester.

摘要翻译： 在批量生产多种类型的半导体器件的情况下设置适当的初始故障筛选条件的方法中，每种类型的器件被少量制造，不考虑每种类型的产品进行加速度测试的步骤， 使用测试半导体器件来估计每种类型的半导体器件市场的故障率。 具体来说，首先，围绕（1）圆）将要开发和批量生产的所有类型的半导体器件分为几组。 {circle around（2）}开发了一种测试半导体器件，其具有与元件的平均数目相同数量的元件，相同的栅极面积，相同的多层布线长度和相同数量的接触孔，平均栅极 面积，平均布线长度和包括在一个类型组中的半导体器件的接触孔的平均数量。 测试半导体器件具有与其对应类型组中包括的类型相同的主要特征（设计规则，MOSFET结构，布线结构等），并且其故障部分（如果有的话）可以通过使用测试仪的分析容易地检测 。

公开(公告)号：US20060220682A1

公开(公告)日：2006-10-05

申请号：US11392359

申请日：2006-03-28

申请人： Youichi Satou ,  Hiroaki Suzuki

发明人： Youichi Satou ,  Hiroaki Suzuki

IPC分类号： H03K19/0175

CPC分类号： H03K3/356165 ,  H03K3/356113

摘要： Differential signals are supplied to gates of first and second transistors. One end and a gate of a third transistor are connected to a signal output node. One end and a gate of a fourth transistor are connected to the other end of the second transistor. A fifth transistor is connected between a power source and the other end of the third transistor. A sixth transistor is connected between a power source and the other end of the fourth transistor. A seventh transistor is inserted between the power source and the signal output node. An eighth transistor is inserted between the power source and the common connection node of the second and fourth transistor, and a gate of the eighth transistor is connected to the gate of the sixth transistor.

摘要翻译： 差分信号被提供给第一和第二晶体管的栅极。 第三晶体管的一端和栅极连接到信号输出节点。 第四晶体管的一端和栅极连接到第二晶体管的另一端。 第五晶体管连接在电源和第三晶体管的另一端之间。 第六晶体管连接在电源和第四晶体管的另一端之间。 第七晶体管插在电源和信号输出节点之间。 第八晶体管被插入在第二和第四晶体管的电源和公共连接节点之间，第八晶体管的栅极连接到第六晶体管的栅极。

公开(公告)号：US06223097B1

公开(公告)日：2001-04-24

申请号：US09265876

申请日：1999-03-11

申请人： Takehiro Hashimoto ,  Yutaka Tanaka ,  Tetsuya Asami ,  Youichi Satou ,  Noriaki Okumiya

发明人： Takehiro Hashimoto ,  Yutaka Tanaka ,  Tetsuya Asami ,  Youichi Satou ,  Noriaki Okumiya

IPC分类号： B07C1700

CPC分类号： H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method for setting appropriate initial-failure screening conditions when mass-producing semiconductor devices of multiple types, devices of each type being manufactured in a small number, the step of subjecting products of every type to an acceleration test is excluded, and instead, the failure ratio on the market of semiconductor devices of each type is estimated using a testing semiconductor device. Specifically, {circle around (1)} first, all types of semiconductor devices to be developed and mass-produced are classified into several groups. {circle around (2)} A test semiconductor device is developed which has the same number of elements, the same gate area, the same multi-layer wiring length and the same number of contact holes as the average number of elements, the average gate area, the average wiring length and the average number of contact holes of the semiconductor devices included in one of the type groups, respectively. The testing semiconductor device has main features (design rules, MOSFET structure, wiring structure, etc.) common to the types included in its corresponding type group, and a failed portion thereof, if any, can be easily detected by an analysis using a tester.

摘要翻译： 在批量生产多种类型的半导体器件的情况下设置适当的初始故障筛选条件的方法中，每种类型的器件被少量制造，不考虑每种类型的产品进行加速度测试的步骤， 使用测试半导体器件来估计每种类型的半导体器件市场的故障率。 具体来说，首先，围绕（1）圆）将要开发和批量生产的所有类型的半导体器件分为几组。 {circle around（2）}开发了一种测试半导体器件，其具有与元件的平均数目相同数量的元件，相同的栅极面积，相同的多层布线长度和相同数量的接触孔，平均栅极 面积，平均布线长度和包括在一个类型组中的半导体器件的接触孔的平均数量。 测试半导体器件具有与其对应类型组中包括的类型相同的主要特征（设计规则，MOSFET结构，布线结构等），并且其故障部分（如果有的话）可以通过使用测试仪的分析容易地检测 。

公开(公告)号：US07123054B2

公开(公告)日：2006-10-17

申请号：US10869328

申请日：2004-06-15

申请人： Youichi Satou ,  Toshikazu Sei ,  Akira Yamaguchi

发明人： Youichi Satou ,  Toshikazu Sei ,  Akira Yamaguchi

IPC分类号： H03K19/0175 ,  H03K19/094 ,  H03K17/16

CPC分类号： H01L27/0262

摘要： A semiconductor integrated circuit device includes a semiconductor integrated circuit formed in a semiconductor chip, and a switching element that is formed in the semiconductor chip and has a current path whose one end and the other end are both connected to the semiconductor integrated circuit. The switching element receives a control signal produced by a control circuit and causes a current to flow from the one end to the other end of the current path by a bipolar operation. The semiconductor integrated circuit device further includes the control circuit that is formed in the semiconductor chip and configured to control a conductive/non-conductive state of the current path of the switching element.

摘要翻译： 半导体集成电路器件包括形成在半导体芯片中的半导体集成电路和形成在半导体芯片中并具有一端和另一端都连接到半导体集成电路的电流通路的开关元件。 开关元件接收由控制电路产生的控制信号，并且通过双极性操作使电流从电流路径的一端流到另一端。 半导体集成电路装置还包括形成在半导体芯片中并被配置为控制开关元件的电流路径的导通/非导通状态的控制电路。

公开(公告)号：US20050047042A1

公开(公告)日：2005-03-03

申请号：US10869328

申请日：2004-06-15

申请人： Youichi Satou ,  Toshikazu Sei ,  Akira Yamaguchi

发明人： Youichi Satou ,  Toshikazu Sei ,  Akira Yamaguchi

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L23/60 ,  H01L27/02 ,  H01L27/10 ,  H02H3/00

CPC分类号： H01L27/0262

摘要： A semiconductor integrated circuit device includes a semiconductor integrated circuit formed in a semiconductor chip, and a switching element that is formed in the semiconductor chip and has a current path whose one end and the other end are both connected to the semiconductor integrated circuit. The switching element receives a control signal produced by a control circuit and causes a current to flow from the one end to the other end of the current path by a bipolar operation. The semiconductor integrated circuit device further includes the control circuit that is formed in the semiconductor chip and configured to control a conductive/non-conductive state of the current path of the switching element.

摘要翻译： 半导体集成电路器件包括形成在半导体芯片中的半导体集成电路和形成在半导体芯片中并具有一端和另一端都连接到半导体集成电路的电流通路的开关元件。 开关元件接收由控制电路产生的控制信号，并且通过双极性操作使电流从电流路径的一端流到另一端。 半导体集成电路装置还包括形成在半导体芯片中并被配置为控制开关元件的电流路径的导通/非导通状态的控制电路。