Plasma processing including asymmetrically grounding a susceptor
    3.
    发明授权
    Plasma processing including asymmetrically grounding a susceptor 有权
    等离子体处理包括不对称接地的感受器

    公开(公告)号:US08877301B2

    公开(公告)日:2014-11-04

    申请号:US13153641

    申请日:2011-06-06

    摘要: An asymmetrically grounded susceptor used in a plasma processing chamber for chemical vapor deposition onto large rectangular panels supported on and grounded by the susceptor. A plurality of grounding straps are connected between the periphery of the susceptor to the grounded vacuum chamber to shorten the grounding paths for RF electrons. Flexible straps allow the susceptor to vertically move. The straps provide a conductance to ground which is asymmetric around the periphery. The straps may be evenly spaced but have different thicknesses or different shapes or be removed from available grounding point and hence provide different RF conductances. The asymmetry is selected to improve the deposition uniformity and other qualities of the PECVD deposited film.

    摘要翻译: 用于等离子体处理室中的不对称接地的基座,用于化学气相沉积到由基座支撑并接地的大矩形面板上。 多个接地带连接在基座的外围与接地的真空室之间,以缩短RF电子的接地路径。 柔性带允许基座垂直移动。 带子提供对周边不对称的地面电导。 带可以是均匀间隔的,但是具有不同的厚度或不同的形状,或者从可用的接地点去除并因此提供不同的RF电导。 选择不对称性以改善PECVD沉积膜的沉积均匀性和其他质量。

    SEMICONDUCTOR DEVICE HAVING LINE-TYPE TRENCH TO DEFINE ACTIVE REGION AND METHOD OF FORMING THE SAME
    4.
    发明申请
    SEMICONDUCTOR DEVICE HAVING LINE-TYPE TRENCH TO DEFINE ACTIVE REGION AND METHOD OF FORMING THE SAME 有权
    具有线型倾斜的半导体器件定义活性区域及其形成方法

    公开(公告)号:US20140117566A1

    公开(公告)日:2014-05-01

    申请号:US13763927

    申请日:2013-02-11

    IPC分类号: H01L23/498

    摘要: A semiconductor device includes a plurality of parallel-trenches that are parallel to each other, a plurality of intersect-trenches that are parallel to each other, a plurality of active regions that are confined by the parallel-trenches and the intersect-trenches, a plurality of lower conductive lines that cross the active regions, a plurality of upper conductive lines that are parallel to each other, that cross the lower conductive lines, and that cross over the active regions, and data storage elements connected to the active regions. Each of the parallel-trenches and the intersect-trenches is a straight line. The parallel-trenches cross the upper conductive lines and form a first acute angle with the upper conductive lines. The intersect-trenches cross the parallel-trenches and form a second acute angle with the parallel-trenches.

    摘要翻译: 半导体器件包括彼此平行的多个平行沟槽,彼此平行的多个相交沟槽,由平行沟槽和交叉沟槽约束的多个有源区域,一个 穿过有源区的多个下导电线,彼此平行的多个上导线,穿过下导电线,并跨越有源区,以及连接到有源区的数据存储元件。 每个平行沟槽和交叉沟槽都是直线。 平行沟槽穿过上导电线并与上导线形成第一锐角。 交叉沟槽与平行沟槽交叉并与平行沟槽形成第二锐角。

    Low temperature co-fired ceramics with low dielectric loss for millimeter-wave application
    5.
    发明授权
    Low temperature co-fired ceramics with low dielectric loss for millimeter-wave application 有权
    用于毫米波应用的低介电损耗的低温共烧陶瓷

    公开(公告)号:US08507393B2

    公开(公告)日:2013-08-13

    申请号:US13098937

    申请日:2011-05-02

    IPC分类号: C03C14/00

    摘要: Provided is a dielectric ceramic composition comprising: 40-70 wt % of a borosilicate-based glass frit comprising 50-80 mol % of SiO2, 15-20 mol % of B2O3, 0.1-5 mol % of one or more alkali metal oxide selected from Li2O and Na2O, and 0.1-30 mol % of one or more alkaline earth metal oxide selected from MgO, CaO, SrO and ZnO; and 30-60 wt % of a ceramic filler represented by Chemical Formula 1: (Zn1-xMgx)2SiO4  (1) wherein 0≦x≦1. The disclosed low temperature co-fired ceramic (LTCC) composition is sinterable at low temperature, with a relative density of at least 95% in the temperature range of 800-900° C., is capable of minimizing electric loss, with a dielectric constant of 4-7 and a very low dielectric loss, and is applicable from the low-frequency band to the millimeter-wave band of 60 GHz or more.

    摘要翻译: 提供一种电介质陶瓷组合物,其包含:40-70重量%的硼硅酸盐基玻璃料,其包含50-80摩尔%的SiO 2,15-20摩尔%的B 2 O 3,0.1-5摩尔%的一种或多种碱金属氧化物 从Li 2 O和Na 2 O,以及0.1-30mol%的一种或多种选自MgO,CaO,SrO和ZnO的碱土金属氧化物; 和30-60重量%的由化学式1表示的陶瓷填料:(Zn1-xMgx)2SiO4(1),其中0≤x≤1。 所公开的低温共烧陶瓷(LTCC)组合物在低温下是可烧结的,在800-900℃的温度范围内相对密度至少为95%,能够最小化电损耗,介电常数 并且具有非常低的介电损耗,并且适用于60GHz以上的低频带至毫米波段。

    Semiconductor device having a device isolation structure
    7.
    发明授权
    Semiconductor device having a device isolation structure 有权
    具有器件隔离结构的半导体器件

    公开(公告)号:US08368169B2

    公开(公告)日:2013-02-05

    申请号:US12897095

    申请日:2010-10-04

    IPC分类号: H01L21/70

    摘要: An example semiconductor device includes a trench formed in a semiconductor substrate to define an active region, a filling dielectric layer provided within the trench, an oxide layer provided between the filling dielectric layer and the trench, a nitride layer provided between the oxide layer and the filling dielectric layer, and a barrier layer provided between the oxide layer and the nitride layer.

    摘要翻译: 示例性半导体器件包括形成在半导体衬底中以限定有源区的沟槽,设置在沟槽内的填充介电层,设置在填充介电层和沟槽之间的氧化物层,设置在氧化物层和 填充介电层,以及设置在氧化物层和氮化物层之间的阻挡层。

    LOW TEMPERATURE CO-FIRED CERAMICS WITH LOW DIELECTRIC LOSS FOR MILLIMETER-WAVE APPLICATION
    9.
    发明申请
    LOW TEMPERATURE CO-FIRED CERAMICS WITH LOW DIELECTRIC LOSS FOR MILLIMETER-WAVE APPLICATION 有权
    用于微波辐射应用的低介电损耗的低温合成陶瓷

    公开(公告)号:US20120202675A1

    公开(公告)日:2012-08-09

    申请号:US13098937

    申请日:2011-05-02

    IPC分类号: C03C14/00

    摘要: Provided is a dielectric ceramic composition comprising: 40-70 wt % of a borosilicate-based glass frit comprising 50-80 mol % of SiO2, 15-20 mol % of B2O3, 0.1-5 mol % of one or more alkali metal oxide selected from Li2O and Na2O, and 0.1-30 mol % of one or more alkaline earth metal oxide selected from MgO, CaO, SrO and ZnO; and 30-60 wt % of a ceramic filler represented by Chemical Formula 1: (Zn1-xMgx)2SiO4  (1) wherein 0≦x≦1. The disclosed low temperature co-fired ceramic (LTCC) composition is sinterable at low temperature, with a relative density of at least 95% in the temperature range of 800-900° C., is capable of minimizing electric loss, with a dielectric constant of 4-7 and a very low dielectric loss, and is applicable from the low-frequency band to the millimeter-wave band of 60 GHz or more.

    摘要翻译: 提供一种电介质陶瓷组合物,其包含:40-70重量%的硼硅酸盐基玻璃料,其包含50-80摩尔%的SiO 2,15-20摩尔%的B 2 O 3,0.1-5摩尔%的一种或多种碱金属氧化物 从Li 2 O和Na 2 O,以及0.1-30mol%的一种或多种选自MgO,CaO,SrO和ZnO的碱土金属氧化物; 和30-60重量%的由化学式1表示的陶瓷填料:(Zn1-xMgx)2SiO4(1)其中0≦̸ x≦̸ 1。 所公开的低温共烧陶瓷(LTCC)组合物在低温下是可烧结的,在800-900℃的温度范围内相对密度至少为95%,能够最小化电损耗,介电常数 并且具有非常低的介电损耗,并且适用于60GHz以上的低频带至毫米波段。

    A-SI SEASONING EFFECT TO IMPROVE SIN RUN-TO-RUN UNIFORMITY
    10.
    发明申请
    A-SI SEASONING EFFECT TO IMPROVE SIN RUN-TO-RUN UNIFORMITY 有权
    A-SI季节效应提高了单机运行的均匀性

    公开(公告)号:US20120040536A1

    公开(公告)日:2012-02-16

    申请号:US13207315

    申请日:2011-08-10

    IPC分类号: H01L21/318

    摘要: Embodiments of the present invention provide methods for depositing a nitrogen-containing material on large-sized substrates disposed in a processing chamber. In one embodiment, a method includes processing a batch of substrates within a processing chamber to deposit a nitrogen-containing material on a substrate from the batch of substrates, and performing a seasoning process at predetermined intervals during processing the batch of substrates to deposit a conductive seasoning layer over a surface of a chamber component disposed in the processing chamber. The chamber component may include a gas distribution plate fabricated from a bare aluminum without anodizing. In one example, the conductive seasoning layer may include amorphous silicon, doped amorphous silicon, doped silicon, doped polysilicon, doped silicon carbide, or the like.

    摘要翻译: 本发明的实施方案提供了在设置在处理室中的大尺寸基板上沉积含氮材料的方法。 在一个实施方案中,一种方法包括处理处理室内的一批衬底,以将一批含有底物的含氮材料从该批衬底上沉积,并在处理该批衬底期间以预定间隔进行调味过程以沉积导电 在处理室中设置的腔室部件的表面上的调味层。 腔室部件可以包括由裸铝制成而不阳极氧化的气体分配板。 在一个示例中,导电调味层可以包括非晶硅,掺杂非晶硅,掺杂硅,掺杂多晶硅,掺杂碳化硅等。