公开(公告)号：US09727674B2

公开(公告)日：2017-08-08

申请号：US14887789

申请日：2015-10-20

Applicant: Jong Eun Koo ,  Young Jin Gu ,  In Youl Lee

Inventor： Jong Eun Koo ,  Young Jin Gu ,  In Youl Lee

IPC: G06F17/50

CPC classification number: G06F17/5009 ,  G06F17/5022 ,  G06F17/5031 ,  G06F17/5036 ,  G06F17/5081 ,  G06F2217/82 ,  G06F2217/84

Abstract: A simulator includes a memory for storing a first netlist, a timing library, and a standard parasitic exchange format (SPEF) file; and a processor configured to compensate for delay to synchronize digital and analog signals. The processor includes a delay calculator module for generating one of a rising time and a falling time and a standard delay format (SDF) file using the first netlist, the timing library, and the SPEF file; an SDF file converter module for adjusting an interconnect delay description included in the SDF file to compensate for delay using the one of the rising time and the falling time; and a digital simulator module for generating an event using a first driving cell according to a compensated interconnect delay description.

公开(公告)号：US20160110483A1

公开(公告)日：2016-04-21

申请号：US14887789

申请日：2015-10-20

Applicant: JONG EUN KOO ,  YOUNG JIN GU ,  IN YOUL LEE

Inventor： JONG EUN KOO ,  YOUNG JIN GU ,  IN YOUL LEE

IPC: G06F17/50

CPC classification number: G06F17/5009 ,  G06F17/5022 ,  G06F17/5031 ,  G06F17/5036 ,  G06F17/5081 ,  G06F2217/82 ,  G06F2217/84

Abstract: A simulator includes a memory for storing a first netlist, a timing library, and a standard parasitic exchange format (SPEF) file; and a processor configured to compensate for delay to synchronize digital and analog signals. The processor includes a delay calculator module for generating one of a rising time and a falling time and a standard delay format (SDF) file using the first netlist, the timing library, and the SPEF file; an SDF file converter module for adjusting an interconnect delay description included in the SDF file to compensate for delay using the one of the rising time and the falling time; and a digital simulator module for generating an event using a first driving cell according to a compensated interconnect delay description.

Abstract translation: 模拟器包括用于存储第一网表，定时库和标准寄生交换格式（SPEF）文件的存储器; 以及被配置为补偿延迟以同步数字和模拟信号的处理器。 该处理器包括用于使用第一网表，定时库和SPEF文件生成上升时间和下降时间之一的延迟计算器模块和标准延迟格式（SDF）文件; SDF文件转换器模块，用于调整包含在SDF文件中的互连延迟描述，以使用上升时间和下降时间之一补偿延迟; 以及数字模拟器模块，用于根据补偿的互连延迟描述使用第一驱动单元产生事件。