公开(公告)号：US20140022855A1

公开(公告)日：2014-01-23

申请号：US13912649

申请日：2013-06-07

申请人： MIN-SOO JANG ,  Young-hun Seo ,  Chan-yong Lee

发明人： MIN-SOO JANG ,  Young-hun Seo ,  Chan-yong Lee

IPC分类号： G11C17/16

CPC分类号： G11C17/16 ,  G11C11/5692 ,  G11C17/18 ,  G11C2211/5624 ,  G11C2211/563

摘要： An antifuse memory device includes an antifuse memory cell, a reference current generation unit, and a comparison unit. The antifuse memory cell includes an antifuse. The reference current generation unit provides a reference current selected from a plurality of reference currents. The comparison unit compares an intensity of a cell current flowing through the antifuse with an intensity of the reference current and provides an output signal corresponding to a result of the comparison.

摘要翻译： 反熔丝存储器件包括反熔丝存储单元，参考电流产生单元和比较单元。 反熔丝存储单元包括反熔丝。 参考电流产生单元提供从多个参考电流中选择的参考电流。 比较单元将流过反熔丝的单元电流的强度与参考电流的强度进行比较，并提供与比较结果相对应的输出信号。

公开(公告)号：US20120224444A1

公开(公告)日：2012-09-06

申请号：US13471592

申请日：2012-05-15

申请人： Kwang-Sook Noh ,  Young-Hun Seo ,  Jong-Hyun Choi

发明人： Kwang-Sook Noh ,  Young-Hun Seo ,  Jong-Hyun Choi

IPC分类号： G11C7/22

CPC分类号： G11C11/402 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40626 ,  G11C2211/4061

摘要： An integrated circuit memory device includes a refresh control circuit that generates an internal memory refresh command signal having a period that is changed relative to a period of an external memory refresh command signal received by the memory device. This change in the period of the internal memory refresh command may be in response to detecting a change in temperature of the memory device. In particular, the refresh control circuit is configured so that the period of the internal memory refresh command signal is increased in response to detecting a reduction in temperature of the memory device.

摘要翻译： 集成电路存储器件包括刷新控制电路，该刷新控制电路产生具有相对于由存储器件接收的外部存储刷新命令信号的周期而改变的周期的内部存储器刷新命令信号。 内部存储器刷新命令的周期中的这种变化可以响应于检测到存储器件的温度变化。 特别地，刷新控制电路被配置为使得响应于检测到存储器件的温度降低而使内部存储器刷新命令信号的周期增加。

公开(公告)号：US07863914B2

公开(公告)日：2011-01-04

申请号：US12003899

申请日：2008-01-03

申请人： Young-hun Seo ,  Won-kyung Chung ,  Han-na Park

发明人： Young-hun Seo ,  Won-kyung Chung ,  Han-na Park

IPC分类号： G01R31/02

CPC分类号： G01R31/31715 ,  G11C29/56 ,  G11C2029/5602

摘要： Example embodiments relate to a semiconductor memory device including a first pad having a probe region and a sensing region, the first pad may be adapted to come in contact with a primary probe, a sensing unit adapted to sense a weak contact of the first pad and the primary probe, the sensing unit may generate an output current in response to a contact point of the primary probe, and a second pad may be adapted to come in contact with a secondary probe to input/output an electric signal. The output current of the sensing unit may be output through the second pad or the secondary probe.

摘要翻译： 示例性实施例涉及包括具有探针区域和感测区域的第一焊盘的半导体存储器件，第一焊盘可以适于与主探针接触，感测单元适于感测第一焊盘的弱接触和 主探头，感测单元可以响应于主探针的接触点而产生输出电流，并且第二焊盘可以适于与辅助探针接触以输入/输出电信号。 感测单元的输出电流可以通过第二垫或辅助探针输出。

公开(公告)号：US07515487B2

公开(公告)日：2009-04-07

申请号：US11567826

申请日：2006-12-07

申请人： Young-Hun Seo ,  Dong-Il Seo ,  Kyu-Chan Lee ,  Jong-Hyun Choi

发明人： Young-Hun Seo ,  Dong-Il Seo ,  Kyu-Chan Lee ,  Jong-Hyun Choi

IPC分类号： G11C5/14

CPC分类号： G11C5/147

摘要： An internal reference voltage generating circuit that reduces a standby current and the number of pins of a semiconductor memory device, in which a reference voltage is provided to an input buffer that receives a signal through an input to which an on die transmitor resistor is connected, includes: a voltage dividing circuit outputting the reference voltage by a power voltage; a pull down driver connected to an end of the voltage dividing circuit; and a calibration control circuit comparing a voltage level of the input and a voltage level of an end of the voltage dividing circuit, and controlling the on resistor value of the pull down driver according to a result of the comparison. The internal reference voltage generating circuit is operated while the memory controller inputs a signal into a mode register set (MRS) to enable the internal reference voltage generating circuit and the output signal of the MRS is activated.

摘要翻译： 一种内部参考电压发生电路，其将待机电流和半导体存储器件的引脚数量减少，其中参考电压被提供给通过连接有管芯发送器电阻器的输入接收信号的输入缓冲器， 包括：分压电路，通过电源电压输出基准电压; 连接到分压电路的一端的下拉驱动器; 以及校正控制电路，比较输入的电压电平和分压电路的端部的电压电平，并根据比较的结果来控制下拉驱动器的导通电阻值。 内部参考电压产生电路在存储器控制器将信号输入到模式寄存器组（MRS）中的情况下操作，以使能内部基准电压产生电路并且MRS的输出信号被激活。

公开(公告)号：US20070152706A1

公开(公告)日：2007-07-05

申请号：US11422856

申请日：2006-06-07

申请人： Young-Hun SEO ,  Jong-Hyun CHOI

发明人： Young-Hun SEO ,  Jong-Hyun CHOI

IPC分类号： H03K19/003

CPC分类号： H03K19/0016

摘要： A semiconductor integrated circuit with low power consumption is provided. In one embodiment, the semiconductor integrated circuit includes a logic circuit portion that is connected between a first power line and a virtual ground line. The logic circuit portion includes at least one NMOS transistor having a first threshold voltage and at least one PMOS transistor having a second threshold voltage. The semiconductor integrated circuit further includes a first MOS transistor, which is connected between the virtual ground line and a ground voltage, where the first MOS transistor has the first threshold voltage and applies the ground voltage to the virtual ground line in an active state. Also included in the semiconductor integrated circuit is a controller that is connected to the first MOS transistor, where the controller applies the ground voltage to the first MOS transistor in the active state and applies a bulk voltage supplied from a bulk power line in a standby state to control a threshold voltage of the first MOS transistor.

摘要翻译： 提供具有低功耗的半导体集成电路。 在一个实施例中，半导体集成电路包括连接在第一电源线和虚拟接地线之间的逻辑电路部分。 逻辑电路部分包括具有第一阈值电压的至少一个NMOS晶体管和具有第二阈值电压的至少一个PMOS晶体管。 半导体集成电路还包括连接在虚拟接地线和接地电压之间的第一MOS晶体管，其中第一MOS晶体管具有第一阈值电压，并将接地电压施加到虚拟接地线处于活动状态。 还包括在半导体集成电路中的控制器是连接到第一MOS晶体管的控制器，其中控制器将该接地电压施加到处于激活状态的第一MOS晶体管，并且将来自大容量电力线的供应的体电压施加在待机状态 以控制第一MOS晶体管的阈值电压。

公开(公告)号：US07224012B2

公开(公告)日：2007-05-29

申请号：US10747111

申请日：2003-12-30

申请人： Young Hun Seo

发明人： Young Hun Seo

IPC分类号： H01L21/8234 ,  H01L21/8242 ,  H01L21/8244 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L28/60 ,  H01L27/0805

摘要： A metal/insulator/metal capacitor and a fabrication method thereof are presented. The method includes forming a first electrode on an insulation film; forming a side wall made of insulating material on a side surface of the first electrode; forming an interlayer insulation film on the top surface of the insulation film including the first electrode and the side wall; forming a via hole to expose the first electrode by selectively etching the interlayer insulation film such that an edge area at which a side surface and a bottom of the via hole intersect is positioned on a top surface of the side wall; forming a dielectric layer on an inner wall of the via hole; forming a second electrode on the dielectric layer such that the via hole is filled; and forming a metal wire on the second electrode such that the metal wire is electrically connected to the second electrode.

摘要翻译： 提出了一种金属/绝缘体/金属电容器及其制造方法。 该方法包括在绝缘膜上形成第一电极; 在所述第一电极的侧表面上形成由绝缘材料制成的侧壁; 在包括第一电极和侧壁的绝缘膜的顶表面上形成层间绝缘膜; 形成通孔，以通过选择性地蚀刻层间绝缘膜来露出第一电极，使得通孔的侧表面和底部相交的边缘区域位于侧壁的顶表面上; 在所述通孔的内壁上形成电介质层; 在所述电介质层上形成第二电极，使得所述通孔被填充; 以及在所述第二电极上形成金属线，使得所述金属线电连接到所述第二电极。

公开(公告)号：US06998324B2

公开(公告)日：2006-02-14

申请号：US10750251

申请日：2003-12-31

申请人： Young Hun Seo

发明人： Young Hun Seo

IPC分类号： H01L21/762

CPC分类号： H01L21/76232 ,  H01L21/76264 ,  H01L21/76283

摘要： Example methods of fabricating a silicon on insulator substrate are disclosed. One example method may include forming a plurality of trenches on a substrate, forming an insulation layer on the trenches, removing a portion of the insulation layer formed on the trenches to partially expose the substrate, and forming a silicon on insulator film in the substrate via the exposed portions of the substrate.

摘要翻译： 公开了制造绝缘体上硅衬底的示例性方法。 一个示例性方法可以包括在衬底上形成多个沟槽，在沟槽上形成绝缘层，去除在沟槽上形成的绝缘层的一部分以部分地暴露衬底，以及在衬底中形成绝缘体上硅膜，通过 衬底的暴露部分。

公开(公告)号：US06995070B2

公开(公告)日：2006-02-07

申请号：US10748045

申请日：2003-12-31

申请人： Young-Hun Seo

发明人： Young-Hun Seo

IPC分类号： H01L21/00

CPC分类号： H01L28/91

摘要： The present invention is directed to a method of fabricating a capacitor having a metal/insulator/metal (MIM) structure, which is capable of providing a minimized semiconductor device with no capacitance variation of a capacitor. According to an aspect of the present invention, a method of fabricating a thin film capacitor comprises the steps of forming a first via and a second via which are isolated with a predetermined distance by selectively etching an interlayer insulating film formed over the entire structure of a semiconductor substrate, filling in the first via and the second via with a first metal material, forming a capacitor window by etching the interlayer insulating film between the first via and the second via to have a predetermined depth, forming a dielectric layer on an inner wall, and forming a second metal material to fill in the capacitor window.

摘要翻译： 本发明涉及一种制造具有金属/绝缘体/金属（MIM）结构的电容器的方法，其能够提供没有电容器的电容变化的最小化的半导体器件。 根据本发明的一个方面，制造薄膜电容器的方法包括以下步骤：通过选择性地蚀刻在整个结构上形成的层间绝缘膜，形成以预定距离隔离的第一通孔和第二通孔 半导体衬底，用第一金属材料填充第一通孔和第二通孔，通过在第一通孔和第二通孔之间蚀刻层间绝缘膜形成电容器窗口以具有预定深度，在内壁上形成电介质层 并且形成第二金属材料以填充电容器窗口。

公开(公告)号：US20050105362A1

公开(公告)日：2005-05-19

申请号：US10954530

申请日：2004-09-29

申请人： Jong-Hyun Choi ,  Dong-Il Seo ,  Young-Hun Seo

发明人： Jong-Hyun Choi ,  Dong-Il Seo ,  Young-Hun Seo

IPC分类号： G11C11/401 ,  G11C11/406 ,  G11C7/00

CPC分类号： G11C11/40618 ,  G11C11/406 ,  G11C11/40622

摘要： A memory device according to the present invention includes multiple refresh modes and a refresh controller. A first refresh mode can respectively select one more memory block among a plurality of banks comprising a plurality of blocks and each of all banks. In addition, the first refresh mode may perform a refresh operation with respect to selected memory blocks. The second refresh mode can select a part of the banks and perform a refresh operation of data with a selected bank. The controller may select one of the first and second refresh modes in a refresh operation.

摘要翻译： 根据本发明的存储器件包括多个刷新模式和刷新控制器。 第一刷新模式可以分别在包括多个块和所有存储体中的每一个的多个存储体中选择一个存储器块。 此外，第一刷新模式可以针对所选择的存储块执行刷新操作。 第二刷新模式可以选择一个存储体的一部分并执行与所选存储体的数据的刷新操作。 控制器可以在刷新操作中选择第一和第二刷新模式之一。

公开(公告)号：US20050047221A1

公开(公告)日：2005-03-03

申请号：US10923729

申请日：2004-08-24

申请人： Jong-Hyun Choi ,  Young-Hun Seo

发明人： Jong-Hyun Choi ,  Young-Hun Seo

IPC分类号： G11C5/14 ,  G11C29/12 ,  G11C5/00

CPC分类号： G11C29/12005 ,  G11C5/147 ,  G11C11/401 ,  G11C29/12 ,  G11C29/50016

摘要： In the negative drop voltage generating apparatus of a semiconductor memory device and the method of controlling a negative voltage generation. The apparatus generates a negative voltage having a level necessary for an operating mode in the semiconductor memory device. The apparatus includes a negative drop voltage generator having first and second output terminals and a voltage separated/integrated unit connected between the first and second output terminals of the negative drop voltage generator. The voltage separated/integrated unit performs a voltage separation and connection so that the negative voltages are generated with individually different levels or with the same level through the first and second output terminals, in response to an applied control signal.

摘要翻译： 在半导体存储器件的负压降电压产生装置中，以及负电压产生的控制方法。 该装置产生具有半导体存储器件中的工作模式所必需的电平的负电压。 该装置包括具有第一和第二输出端的负压降电压发生器和连接在负压降电压发生器的第一和第二输出端之间的电压分离/集成单元。 电压分离/集成单元执行电压分离和连接，以响应于所施加的控制信号，通过第一和第二输出端子以单独不同的电平或相同的电平产生负电压。