公开(公告)号：US09457713B2

公开(公告)日：2016-10-04

申请号：US13817514

申请日：2010-10-01

申请人： Young Pil Kim ,  Byeong Gil An

发明人： Young Pil Kim ,  Byeong Gil An

IPC分类号： B60Q11/00 ,  B60Q3/06

CPC分类号： B60Q3/30

摘要： Herein, there is disclosed an LED illuminator installed to illuminate an inner space of a hood of a vehicle when the hood is open. The LED illuminator comprises a protection frame positioned in an inner space of the hood; and an LED module having a light emitting portion, wherein the light emitting portion is installed to be concealed into and exposed to the outside of the protection frame.

摘要翻译： 这里，公开了一种LED照明器，其安装成在发动机罩打开时照亮车辆的发动机罩的内部空间。 LED照明器包括位于罩的内部空间中的保护框架; 以及具有发光部分的LED模块，其中所述发光部分被安装以隐藏并暴露于所述保护框架的外部。

公开(公告)号：US08638597B2

公开(公告)日：2014-01-28

申请号：US13476368

申请日：2012-05-21

申请人： Chulmin Jung ,  Yong Lu ,  Kang Yong Kim ,  Young Pil Kim

发明人： Chulmin Jung ,  Yong Lu ,  Kang Yong Kim ,  Young Pil Kim

IPC分类号： G11C11/00

CPC分类号： G11C7/14 ,  G11C7/02 ,  G11C7/04 ,  G11C7/062 ,  G11C11/1673

摘要： A memory array includes a plurality of magneto-resistive changing memory cells. Each resistive changing memory cell is electrically between a source line and a bit line and a transistor electrically between the resistive changing memory cell and the bit line. The transistor has a gate electrically between a source region and a drain region and the source region being electrically between the r magneto-resistive changing memory cell and the gate. A word line is electrically coupled to the gate. A bit line charge accumulation sensing for magneto-resistive changing memory is also disclosed.

摘要翻译： 存储器阵列包括多个磁阻改变存储单元。 每个电阻变化存储单元在电源线和位线之间电连接，并且电阻在电阻变化存储单元和位线之间。 晶体管在源极区域和漏极区域之间具有电门，并且源极区域电连接在r磁阻变化存储器单元和栅极之间。 字线电耦合到门。 还公开了用于磁阻改变存储器的位线电荷累积感测。

公开(公告)号：US08617952B2

公开(公告)日：2013-12-31

申请号：US12891966

申请日：2010-09-28

申请人： Young Pil Kim ,  Hyung-Kew Lee ,  Peter Nicholas Manos ,  Chulmin Jung ,  Maroun Georges Khoury ,  Dadi Setiadi

发明人： Young Pil Kim ,  Hyung-Kew Lee ,  Peter Nicholas Manos ,  Chulmin Jung ,  Maroun Georges Khoury ,  Dadi Setiadi

IPC分类号： H01L21/336

CPC分类号： H01L45/1233 ,  H01L27/228 ,  H01L27/2454 ,  H01L45/1206

摘要： A method includes providing a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer. Each pillar structure forms a vertical pillar transistor having a top surface and a side surface orthogonal to the top surface. Then a hardening species is implanted into the vertical pillar transistor top surface. Then the vertical pillar transistor side surface is oxidized to form a side surface oxide layer. The side surface oxide layer is removed to form vertical pillar transistor having rounded side surfaces.

摘要翻译： 一种方法包括提供具有从半导体晶片正交延伸的多个柱结构的半导体晶片。 每个柱结构形成具有与顶表面正交的顶表面和侧表面的垂直柱状晶体管。 然后将硬化物质注入垂直柱晶体管顶表面。 然后，垂直柱状晶体管侧面被氧化，形成侧面氧化层。 去除侧面氧化物层以形成具有圆形侧表面的垂直柱状晶体管。

公开(公告)号：US20120230094A1

公开(公告)日：2012-09-13

申请号：US13476368

申请日：2012-05-21

申请人： Chulmin Jung ,  Yong Lu ,  Kang Yong Kim ,  Young Pil Kim

发明人： Chulmin Jung ,  Yong Lu ,  Kang Yong Kim ,  Young Pil Kim

IPC分类号： G11C11/16

CPC分类号： G11C7/14 ,  G11C7/02 ,  G11C7/04 ,  G11C7/062 ,  G11C11/1673

摘要： A memory array includes a plurality of magneto-resistive changing memory cells. Each resistive changing memory cell is electrically between a source line and a bit line and a transistor electrically between the resistive changing memory cell and the bit line. The transistor has a gate electrically between a source region and a drain region and the source region being electrically between the r magneto-resistive changing memory cell and the gate. A word line is electrically coupled to the gate. A bit line charge accumulation sensing for magneto-resistive changing memory is also disclosed.

摘要翻译： 存储器阵列包括多个磁阻改变存储单元。 每个电阻变化存储单元在电源线和位线之间电连接，并且电阻在电阻变化存储单元和位线之间。 晶体管在源极区域和漏极区域之间具有电门，并且源极区域电连接在r磁阻变化存储器单元和栅极之间。 字线电耦合到门。 还公开了用于磁阻改变存储器的位线电荷累积感测。

公开(公告)号：US08218360B2

公开(公告)日：2012-07-10

申请号：US12582880

申请日：2009-10-21

申请人： Kwang-Jin Lee ,  Young-kug Moon ,  Young-pil Kim

发明人： Kwang-Jin Lee ,  Young-kug Moon ,  Young-pil Kim

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C13/004 ,  G11C7/1018 ,  G11C8/18 ,  G11C11/5678 ,  G11C13/00 ,  G11C13/0004

摘要： Phase-change and resistance-change random access memory devices are provided which include a phase-change or resistance-change memory cell array and a sense amplifier that is configured to amplify data read from the phase-change memory cell array. These random access memory devices are configured to read data from a first word line of the phase-change or resistance-change memory cell array and to insert a dummy burst in which no data is read when a first boundary crossing occurs during a burst mode operation. Related methods of operating phase-change and/or resistance-change random access memory devices in burst mode are also provided.

摘要翻译： 提供了相变和电阻变化随机存取存储器件，其包括相变或电阻变化存储单元阵列和被配置为放大从相变存储单元阵列读取的数据的读出放大器。 这些随机存取存储器件被配置为从相变或电阻变化存储单元阵列的第一字线读取数据，并且在突发模式操作期间发生第一边界交叉时插入其中没有读取数据的虚拟脉冲串 。 还提供了以突发模式操作相变和/或电阻变化随机存取存储器件的相关方法。

公开(公告)号：US08158964B2

公开(公告)日：2012-04-17

申请号：US12502221

申请日：2009-07-13

申请人： Young Pil Kim ,  Nurul Amin ,  Dadi Setiadi ,  Venugopalan Vaithyanathan ,  Wei Tian ,  Insik Jin

发明人： Young Pil Kim ,  Nurul Amin ,  Dadi Setiadi ,  Venugopalan Vaithyanathan ,  Wei Tian ,  Insik Jin

IPC分类号： H01L29/02 ,  H01L29/47

CPC分类号： H01L27/0814 ,  G11C11/161 ,  G11C11/1659 ,  G11C13/0002 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/11507 ,  H01L27/1203 ,  H01L27/224 ,  H01L27/2409 ,  H01L29/66143 ,  H01L29/66212 ,  H01L29/872 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/14 ,  H01L45/143 ,  H01L45/146 ,  H01L45/147

摘要： A switching element that includes a first semiconductor layer, the first semiconductor layer having a first portion and a second portion; a second semiconductor layer, the second semiconductor layer having a first portion and a second portion; an insulating layer disposed between the first semiconductor layer and the second semiconductor layer; a first metal contact in contact with the first portion of the first semiconductor layer forming a first junction and in contact with the first portion of the second semiconductor layer forming a second junction; a second metal contact in contact with the second portion of the first semiconductor layer forming a third junction and in contact with the second portion of the second semiconductor layer forming a fourth junction, wherein the first junction and the fourth junction are Schottky contacts, and the second junction and the third junction are ohmic contacts.

公开(公告)号：US20120074488A1

公开(公告)日：2012-03-29

申请号：US12891966

申请日：2010-09-28

申请人： Young Pil Kim ,  Hyung-Kyu Lee ,  Peter Nicholas Manos ,  Chulmin Jung ,  Maroun Georges Khoury ,  Dadi Setiadi

发明人： Young Pil Kim ,  Hyung-Kyu Lee ,  Peter Nicholas Manos ,  Chulmin Jung ,  Maroun Georges Khoury ,  Dadi Setiadi

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L45/1233 ,  H01L27/228 ,  H01L27/2454 ,  H01L45/1206

摘要： A method includes providing a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer. Each pillar structure forms a vertical pillar transistor having a top surface and a side surface orthogonal to the top surface. Then a hardening species is implanted into the vertical pillar transistor top surface. Then the vertical pillar transistor side surface is oxidized to form a side surface oxide layer. The side surface oxide layer is removed to form vertical pillar transistor having rounded side surfaces.

摘要翻译： 一种方法包括提供具有从半导体晶片正交延伸的多个柱结构的半导体晶片。 每个柱结构形成具有与顶表面正交的顶表面和侧表面的垂直柱晶体管。 然后将硬化物质注入垂直柱晶体管顶表面。 然后，垂直柱状晶体管侧面被氧化，形成侧面氧化层。 去除侧面氧化物层以形成具有圆形侧表面的垂直柱状晶体管。

公开(公告)号：US08119486B2

公开(公告)日：2012-02-21

申请号：US12984176

申请日：2011-01-04

申请人： Young-Pil Kim ,  Eun-Ae Chung ,  Gab-Jin Nam ,  Hee-Don Hwang ,  Ji-Young Min

发明人： Young-Pil Kim ,  Eun-Ae Chung ,  Gab-Jin Nam ,  Hee-Don Hwang ,  Ji-Young Min

IPC分类号： H01L21/336

CPC分类号： H01L27/10876 ,  H01L29/66628

摘要： A method according to example embodiments includes forming isolation regions in a substrate, the isolation regions defining active regions. Desired regions of the active regions and the isolation regions are removed, thereby forming recess channel trenches to a desired depth. The recess channel trenches are fog to have a first region in contact with the active regions and a second region in contact with the isolation regions. A width of a bottom surface of the recess channel trenches is less than that of a top surface thereof. The active regions and the isolation regions are annealed to uplift the bottom surface of the recess channel trenches. An area of the bottom surface of the first region is increased. A depth of the bottom surface of the first region is reduced.

摘要翻译： 根据示例实施例的方法包括在衬底中形成隔离区域，所述隔离区限定活性区域。 去除有源区域和隔离区域的期望区域，从而形成凹槽沟槽到期望的深度。 凹槽沟槽是雾化的，以具有与活性区域接触的第一区域和与隔离区域接触的第二区域。 凹槽沟槽的底面的宽度小于其顶面的宽度。 有源区域和隔离区域被退火以提高凹槽通道沟槽的底面。 第一区域的底面的面积增加。 第一区域的底面的深度减小。

公开(公告)号：US20120039111A1

公开(公告)日：2012-02-16

申请号：US13278334

申请日：2011-10-21

申请人： Chulmin Jung ,  Maroun Georges Khoury ,  Yong Lu ,  Young Pil Kim

发明人： Chulmin Jung ,  Maroun Georges Khoury ,  Yong Lu ,  Young Pil Kim

IPC分类号： G11C11/00 ,  H01L29/78 ,  H01L45/00

CPC分类号： G11C11/16 ,  G11C11/1659 ,  H01L27/228 ,  H01L29/1083

摘要： A memory unit includes a resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell and a semiconductor transistor in electrical connection with the resistive sense memory cell. The semiconductor transistor includes a gate element formed on a substrate. The semiconductor transistor includes a source contact and a bit contact. The gate element electrically connects the source contact and the bit contact. The resistive sense memory cell electrically is connected to the bit contact. The source contact is more heavily implanted with dopant material then the bit contact.

摘要翻译： 存储单元包括电阻读出存储单元，配置为在通过电阻读出存储单元的电流和与电阻读出存储单元电连接的半导体晶体管时，在高电阻状态和低电阻状态之间切换。 半导体晶体管包括形成在基板上的栅极元件。 半导体晶体管包括源极触点和位触点。 门元件电连接源触点和触点触点。 电阻读出存储单元电连接到位触点。 源触点被更多地注入掺杂剂材料，然后进行位接触。

公开(公告)号：US08072014B2

公开(公告)日：2011-12-06

申请号：US12903301

申请日：2010-10-13

申请人： Chulmin Jung ,  Maroun Georges Khoury ,  Yong Lu ,  Young Pil Kim

发明人： Chulmin Jung ,  Maroun Georges Khoury ,  Yong Lu ,  Young Pil Kim

IPC分类号： G11C11/00 ,  H01L29/78

CPC分类号： G11C11/16 ,  G11C11/1659 ,  H01L27/228 ,  H01L29/1083

摘要： A memory unit includes a resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell and a semiconductor transistor in electrical connection with the resistive sense memory cell. The semiconductor transistor includes a gate element formed on a substrate. The semiconductor transistor includes a source contact and a bit contact. The gate element electrically connects the source contact and the bit contact. The resistive sense memory cell electrically is connected to the bit contact. The source contact is more heavily implanted with dopant material then the bit contact.

摘要翻译： 存储单元包括电阻读出存储单元，配置为在通过电阻读出存储单元的电流和与电阻读出存储单元电连接的半导体晶体管时，在高电阻状态和低电阻状态之间切换。 半导体晶体管包括形成在基板上的栅极元件。 半导体晶体管包括源极触点和位触点。 门元件电连接源触点和触点触点。 电阻读出存储单元电连接到位触点。 源触点被更多地注入掺杂剂材料，然后进行位接触。