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14 条记录 (耗时 0.019 秒)

    Semiconductor memory device and method thereof
    3.
    发明授权
    Semiconductor memory device and method thereof 失效
    半导体存储器件及其方法

    公开(公告)号：US07755958B2

    公开(公告)日：2010-07-13

    申请号：US11878087

    申请日：2007-07-20

    申请人： Young-yong Byun ,  Hi-choon Lee

    发明人： Young-yong Byun ,  Hi-choon Lee

    IPC分类号： G11C29/00

    CPC分类号： G11C29/40

    摘要： A semiconductor memory device and method thereof are provided. The example semiconductor memory device may include a plurality of comparators receiving output data signals from each of a plurality of sub-array blocks, comparing the output data signals from each of the plurality of sub-array blocks and outputting a plurality of comparison result signals and a test circuit receiving the plurality of comparison result signals from the plurality of comparators, respectively, the test circuit configured to selectively output one of a given one of the plurality of comparison result signals on a given data input/output pad and a given signal obtained by performing a logical operation on at least two of the plurality of comparison result signals on the given data input/output pad in response to a select signal.

    摘要翻译： 提供一种半导体存储器件及其方法。 示例性半导体存储器件可以包括多个比较器，其从多个子阵列块中的每一个接收输出数据信号，比较来自多个子阵列块中的每一个的输出数据信号并输出​​多个比较结果信号;以及 测试电路分别从多个比较器接收多个比较结果信号，该测试电路被配置为在给定的数据输入/输出焊盘上选择性地输出多个比较结果信号中给定的一个中的一个，以及获得的给定信号 通过响应于选择信号对给定数据输入/输出焊盘上的多个比较结果信号中的至少两个进行逻辑运算。

    Semiconductor memory device and method thereof
    5.
    发明申请
    Semiconductor memory device and method thereof 失效
    半导体存储器件及其方法

    公开(公告)号：US20080089153A1

    公开(公告)日：2008-04-17

    申请号：US11878087

    申请日：2007-07-20

    申请人： Young-yong Byun ,  Hi-choon Lee

    发明人： Young-yong Byun ,  Hi-choon Lee

    IPC分类号： G11C29/04

    CPC分类号： G11C29/40

    摘要： A semiconductor memory device and method thereof are provided. The example semiconductor memory device may include a plurality of comparators receiving output data signals from each of a plurality of sub-array blocks, comparing the output data signals from each of the plurality of sub-array blocks and outputting a plurality of comparison result signals and a test circuit receiving the plurality of comparison result signals from the plurality of comparators, respectively, the test circuit configured to selectively output one of a given one of the plurality of comparison result signals on a given data input/output pad and a given signal obtained by performing a logical operation on at least two of the plurality of comparison result signals on the given data input/output pad in response to a select signal.

    摘要翻译： 提供一种半导体存储器件及其方法。 示例性半导体存储器件可以包括多个比较器，其从多个子阵列块中的每一个接收输出数据信号，比较来自多个子阵列块中的每一个的输出数据信号并输出​​多个比较结果信号;以及 测试电路分别从多个比较器接收多个比较结果信号，该测试电路被配置为在给定的数据输入/输出焊盘上选择性地输出多个比较结果信号中给定的一个中的一个，以及获得的给定信号 通过响应于选择信号对给定数据输入/输出焊盘上的多个比较结果信号中的至少两个进行逻辑运算。

    Word line driving circuit and method
    6.
    发明授权
    Word line driving circuit and method 有权
    字线驱动电路及方法

    公开(公告)号：US08228755B2

    公开(公告)日：2012-07-24

    申请号：US12695213

    申请日：2010-01-28

    申请人： Hyun-Ho Park ,  Young-Yong Byun ,  Yamada Satoru

    发明人： Hyun-Ho Park ,  Young-Yong Byun ,  Yamada Satoru

    IPC分类号： G11C7/00

    CPC分类号： G11C8/08 ,  G11C11/4085

    摘要： A word line driving circuit includes an address decoding signal generating unit and a word line voltage supply unit. The address decoding signal generating unit includes inverter chain receiving and delaying a first address decoding signal and outputting the delayed first address decoding signal. The word line voltage supply unit includes a pull-up driver that supplies the delayed first address signal to a selected word line in response to a second address decoding signal. The inverter chain includes an NMOS transistor outputting the delayed first address signal and a source terminal of the NMOS transistor receives a set voltage that is higher than a ground voltage and lower than a high voltage.

    摘要翻译： 字线驱动电路包括地址解码信号产生单元和字线电压提供单元。 地址解码信号发生单元包括反相器链接收和延迟第一地址解码信号并输出​​延迟的第一地址解码信号。 字线电压供给单元包括上拉驱动器，其响应于第二地址解码信号将延迟的第一地址信号提供给所选择的字线。 逆变器链包括输出延迟的第一地址信号的NMOS晶体管，并且NMOS晶体管的源极端子接收高于接地电压并低于高电压的设定电压。

    WORD LINE DRIVING CIRCUIT AND METHOD
    7.
    发明申请
    WORD LINE DRIVING CIRCUIT AND METHOD 有权
    字线驱动电路及方法

    公开(公告)号：US20100202241A1

    公开(公告)日：2010-08-12

    申请号：US12695213

    申请日：2010-01-28

    申请人： Hyun-Ho PARK ,  Young-Yong BYUN ,  Yamada SATORU

    发明人： Hyun-Ho PARK ,  Young-Yong BYUN ,  Yamada SATORU

    IPC分类号： G11C8/08

    CPC分类号： G11C8/08 ,  G11C11/4085

    摘要： A word line driving circuit includes an address decoding signal generating unit and a word line voltage supply unit. The address decoding signal generating unit includes inverter chain receiving and delaying a first address decoding signal and outputting the delayed first address decoding signal. The word line voltage supply unit includes a pull-up driver that supplies the delayed first address signal to a selected word line in response to a second address decoding signal. The inverter chain includes an NMOS transistor outputting the delayed first address signal and a source terminal of the NMOS transistor receives a set voltage that is higher than a ground voltage and lower than a high voltage.

    摘要翻译： 字线驱动电路包括地址解码信号产生单元和字线电压提供单元。 地址解码信号发生单元包括反相器链接收和延迟第一地址解码信号并输出​​延迟的第一地址解码信号。 字线电压供给单元包括上拉驱动器，其响应于第二地址解码信号将延迟的第一地址信号提供给所选择的字线。 逆变器链包括输出延迟的第一地址信号的NMOS晶体管，并且NMOS晶体管的源极端子接收高于接地电压并低于高电压的设定电压。

    SEMICONDUCTOR MEMORY DEVICE, METHOD OF PERFORMING A REFRESH FOR SEMICONDUCTOR MEMORY DEVICE AND REFRESH COUNTER IN SEMICONDUCTOR MEMORY DEVICE
    8.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE, METHOD OF PERFORMING A REFRESH FOR SEMICONDUCTOR MEMORY DEVICE AND REFRESH COUNTER IN SEMICONDUCTOR MEMORY DEVICE 有权
    半导体存储器件，半导体存储器件中的半导体存储器件和复位计数器的刷新方法

    公开(公告)号：US20160027492A1

    公开(公告)日：2016-01-28

    申请号：US14723261

    申请日：2015-05-27

    申请人： Young-Yong BYUN ,  Whi-Young BAE

    发明人： Young-Yong BYUN ,  Whi-Young BAE

    IPC分类号： G11C11/406 ,  G11C11/408

    CPC分类号： G11C11/40618 ,  G11C8/04 ,  G11C8/10 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/408

    摘要： A semiconductor memory device may include a memory cell array, a first decoder and a second decoder. The memory cell array includes a plurality of memory cell rows. The first decoder is configured to select a first number of memory cell rows of the plurality of memory cell rows based on a selected refresh row address of a set of row addresses. The second decoder is configured to select a second number of memory cell rows of the plurality of memory cell rows based on the selected refresh row address. A total number of the first number and the second number is varied in response to the selected refresh row address.

    摘要翻译： 半导体存储器件可以包括存储单元阵列，第一解码器和第二解码器。 存储单元阵列包括多个存储单元行。 第一解码器被配置为基于一组行地址的选择的刷新行地址来选择多个存储单元行的第一数量的存储单元行。 第二解码器被配置为基于所选择的刷新行地址来选择多个存储单元行的第二数量的存储单元行。 响应于所选择的刷新行地址，第一号码和第二号码的总数变化。

    SEMICONDUCTOR MEMORY DEVICE FOR CONTROLLING HAVING DIFFERENT REFRESH OPERATION PERIODS FOR DIFFERENT SETS OF MEMORY CELLS
    9.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE FOR CONTROLLING HAVING DIFFERENT REFRESH OPERATION PERIODS FOR DIFFERENT SETS OF MEMORY CELLS 审中-公开
    用于控制不同存储器组的不同刷新操作期的半导体存储器件

    公开(公告)号：US20160005452A1

    公开(公告)日：2016-01-07

    申请号：US14722634

    申请日：2015-05-27

    申请人： Whi-Young BAE ,  Young-Sik KIM ,  Young-Yong BYUN

    发明人： Whi-Young BAE ,  Young-Sik KIM ,  Young-Yong BYUN

    IPC分类号： G11C11/406 ,  G06F11/10 ,  G11C11/408 ,  G11C29/00 ,  G11C11/4076

    CPC分类号： G11C11/406 ,  G06F11/1048 ,  G11C11/40611 ,  G11C11/408 ,  G11C29/24 ,  G11C29/70 ,  G11C29/783 ,  G11C29/816 ,  G11C2029/0411 ,  G11C2211/4061

    摘要： Provided is a semiconductor memory device for controlling a refresh operation of redundancy memory cells. The semiconductor memory device may include normal memory cells and redundancy memory cells that are used to repair normal memory cell(s) to which a defective cell is connected, and an error-correction code (ECC) memory cell row that stores parity bits for controlling the defective cell. Memory cells on the normal memory cell rows are refreshed during a first refresh cycle. Other memory cells on, such as redundancy memory cell rows, an edge memory cell row that is adjacent to the redundancy memory cell row(s) from among the normal memory cell rows, and/or the ECC memory cell row may be refreshed during a second refresh cycle that is different from the first refresh cycle.

    摘要翻译： 提供了一种用于控制冗余存储单元的刷新操作的半导体存储器件。 半导体存储器件可以包括用于修复连接有缺陷单元的正常存储单元的正常存储器单元和冗余存储单元，以及存储用于控制的奇偶校验位的纠错码（ECC）存储单元行 有缺陷的单元格。 正常存储单元行中的存储单元在第一次刷新周期期间刷新。 诸如冗余存储器单元行之间的其它存储单元，与普通存储单元行中的冗余存储器单元行相邻的边沿存储单元行和/或ECC存储单元行可以在 与第一刷新周期不同的第二刷新周期。

    Delay locked loop circuit having coarse lock time adaptive to frequency band and semiconductor memory device having the delay locked loop circuit
    10.
    发明授权
    Delay locked loop circuit having coarse lock time adaptive to frequency band and semiconductor memory device having the delay locked loop circuit 失效
    具有自适应频带的粗锁定时间的延迟锁定环路电路和具有延迟锁相环电路的半导体存储器件

    公开(公告)号：US07656207B2

    公开(公告)日：2010-02-02

    申请号：US12009080

    申请日：2008-01-16

    申请人： Young-yong Byun

    发明人： Young-yong Byun

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0812 ,  H03L7/085 ,  H03L7/10

    摘要： Provided are a DLL circuit having a coarse lock time adaptive to a frequency band of an external clock signal and a semiconductor memory device having the DLL circuit. The DLL circuit includes a delay circuit, a replica circuit, and a phase detector. The phase detector generates a first comparison signal used by the delay circuit to delay an external clock signal in units of a first cell delay time or a second comparison signal used by the delay circuit to delay the external clock signal in units of a second cell delay time. The DLL circuit delays the external clock signal by the cell delay time adaptive to the frequency band of the external clock signal, and thus can perform an accurate and rapid coarse lock operation for the entire frequency band.

    摘要翻译： 提供一种具有适应于外部时钟信号的频带的粗略锁定时间的DLL电路和具有该DLL电路的半导体存储器件。 DLL电路包括延迟电路，复制电路和相位检测器。 相位检测器产生由延迟电路使用的第一比较信号，以以第一单元延迟时间为单位延迟外部时钟信号或延迟电路使用的第二比较信号，以以第二单元延迟为单位延迟外部时钟信号 时间。 DLL电路将外部时钟信号延迟自适应外部时钟信号的频带的单元延迟时间，从而可以对整个频带执行准确和快速的粗略锁定操作。