公开(公告)号：US07936002B2

公开(公告)日：2011-05-03

申请号：US12456391

申请日：2009-06-16

申请人： Jonghyuk Kim ,  Han-Soo Kim ,  YoungSeop Rah ,  Min-sung Song ,  Jang Young Chul ,  Soon-Moon Jung ,  Wonseok Cho

发明人： Jonghyuk Kim ,  Han-Soo Kim ,  YoungSeop Rah ,  Min-sung Song ,  Jang Young Chul ,  Soon-Moon Jung ,  Wonseok Cho

IPC分类号： H01L29/76 ,  H01L31/036 ,  H01L31/112 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L21/82385 ,  H01L21/8221 ,  H01L21/823425 ,  H01L21/823456 ,  H01L21/823468 ,  H01L23/481 ,  H01L23/485 ,  H01L27/0688 ,  H01L27/11526 ,  H01L27/11551 ,  H01L2224/9202 ,  H01L21/76898

摘要： In multiple-layered memory devices, memory systems employing the same, and methods of forming such devices, a second memory device layer on a first memory device layer comprises a second substrate including a second memory cell region. The second substrate includes only a single well in the second memory cell region, the single well of the second memory cell region comprising a semiconducting material doped with impurity of one of a first type and second type. The single well defines an active region in the second memory cell region of the second substrate. Multiple second cell strings are arranged on the second substrate in the second active region. Although the second memory cell region includes only a single well, during a programming or erase operation of the memory cells of the second layer, requiring a high voltage to be applied to the single well in the substrate of the second layer, the high voltage will not interfere with the operation of the peripheral transistors of the first layer, second layer, or other layers, since they are isolated from each other. As a result, the substrate of the second layer can be prepared to have a thinner profile, and with fewer processing steps, resulting in devices with higher-density, greater reliability, and reduced fabrication costs.

摘要翻译： 在多层存储器件中，采用该器件的存储器系统和形成这种器件的方法在第一存储器件层上的第二存储器件层包括包括第二存储单元区域的第二衬底。 第二衬底仅包括第二存储单元区域中的单个阱，第二存储单元区域的单阱包括掺杂有第一类型和第二类型之一杂质的半导体材料。 单阱限定了第二衬底的第二存储单元区域中的有源区。 多个第二电池串被布置在第二有源区域中的第二衬底上。 虽然第二存储单元区域仅包括单个阱，但是在第二层的存储单元的编程或擦除操作期间，需要向第二层的衬底中的单个阱施加高电压，高电压将 不妨碍第一层，第二层或其它层的外围晶体管的操作，因为它们彼此隔离。 结果，第二层的基底可以被制备成具有更薄的轮廓，并且具有更少的加工步骤，导致具有更高密度，更高可靠性和降低制造成本的装置。

公开(公告)号：US08227306B2

公开(公告)日：2012-07-24

申请号：US13069869

申请日：2011-03-23

申请人： Jonghyuk Kim ,  Han-Soo Kim ,  YoungSeop Rah ,  Min-sung Song ,  Jang Young Chul ,  Soon-Moon Jung ,  Wonseok Cho

发明人： Jonghyuk Kim ,  Han-Soo Kim ,  YoungSeop Rah ,  Min-sung Song ,  Jang Young Chul ,  Soon-Moon Jung ,  Wonseok Cho

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/82385 ,  H01L21/8221 ,  H01L21/823425 ,  H01L21/823456 ,  H01L21/823468 ,  H01L23/481 ,  H01L23/485 ,  H01L27/0688 ,  H01L27/11526 ,  H01L27/11551 ,  H01L2224/9202 ,  H01L21/76898

摘要： In multiple-layered memory devices, memory systems employing the same, and methods of forming such devices, a second memory device layer on a first memory device layer comprises a second substrate including a second memory cell region. The second substrate includes only a single well in the second memory cell region, the single well of the second memory cell region comprising a semiconducting material doped with impurity of one of a first type and second type. The single well defines an active region in the second memory cell region of the second substrate. Multiple second cell strings are arranged on the second substrate in the second active region. Although the second memory cell region includes only a single well, during a programming or erase operation of the memory cells of the second layer, requiring a high voltage to be applied to the single well in the substrate of the second layer, the high voltage will not interfere with the operation of the peripheral transistors of the first layer, second layer, or other layers, since they are isolated from each other. As a result, the substrate of the second layer can be prepared to have a thinner profile, and with fewer processing steps, resulting in devices with higher-density, greater reliability, and reduced fabrication costs.

摘要翻译： 在多层存储器件中，采用该器件的存储器系统和形成这种器件的方法在第一存储器件层上的第二存储器件层包括包括第二存储单元区域的第二衬底。 第二衬底仅包括第二存储单元区域中的单个阱，第二存储单元区域的单阱包括掺杂有第一类型和第二类型之一杂质的半导体材料。 单阱限定了第二衬底的第二存储单元区域中的有源区。 多个第二电池串被布置在第二有源区域中的第二衬底上。 虽然第二存储单元区域仅包括单个阱，但是在第二层的存储单元的编程或擦除操作期间，需要向第二层的衬底中的单个阱施加高电压，高电压将 不妨碍第一层，第二层或其它层的外围晶体管的操作，因为它们彼此隔离。 结果，第二层的基底可以被制备成具有更薄的轮廓，并且具有更少的加工步骤，导致具有更高密度，更高可靠性和降低制造成本的装置。

公开(公告)号：US20110171787A1

公开(公告)日：2011-07-14

申请号：US13069869

申请日：2011-03-23

申请人： Jonghyuk Kim ,  Han-Soo Kim ,  YoungSeop Rah ,  Min-sung Song ,  Jang Young Chul ,  Soon-Moon Jung ,  Wonseok Cho

发明人： Jonghyuk Kim ,  Han-Soo Kim ,  YoungSeop Rah ,  Min-sung Song ,  Jang Young Chul ,  Soon-Moon Jung ,  Wonseok Cho

IPC分类号： H01L21/8246

CPC分类号： H01L21/82385 ,  H01L21/8221 ,  H01L21/823425 ,  H01L21/823456 ,  H01L21/823468 ,  H01L23/481 ,  H01L23/485 ,  H01L27/0688 ,  H01L27/11526 ,  H01L27/11551 ,  H01L2224/9202 ,  H01L21/76898

摘要： In multiple-layered memory devices, memory systems employing the same, and methods of forming such devices, a second memory device layer on a first memory device layer comprises a second substrate including a second memory cell region. The second substrate includes only a single well in the second memory cell region, the single well of the second memory cell region comprising a semiconducting material doped with impurity of one of a first type and second type. The single well defines an active region in the second memory cell region of the second substrate. Multiple second cell strings are arranged on the second substrate in the second active region. Although the second memory cell region includes only a single well, during a programming or erase operation of the memory cells of the second layer, requiring a high voltage to be applied to the single well in the substrate of the second layer, the high voltage will not interfere with the operation of the peripheral transistors of the first layer, second layer, or other layers, since they are isolated from each other. As a result, the substrate of the second layer can be prepared to have a thinner profile, and with fewer processing steps, resulting in devices with higher-density, greater reliability, and reduced fabrication costs.

摘要翻译： 在多层存储器件中，采用该器件的存储器系统和形成这种器件的方法在第一存储器件层上的第二存储器件层包括包括第二存储单元区域的第二衬底。 第二衬底仅包括第二存储单元区域中的单个阱，第二存储单元区域的单阱包括掺杂有第一类型和第二类型之一杂质的半导体材料。 单阱限定了第二衬底的第二存储单元区域中的有源区。 多个第二电池串被布置在第二有源区域中的第二衬底上。 虽然第二存储单元区域仅包括单个阱，但是在第二层的存储单元的编程或擦除操作期间，需要向第二层的衬底中的单个阱施加高电压，高电压将 不妨碍第一层，第二层或其它层的外围晶体管的操作，因为它们彼此隔离。 结果，第二层的基底可以被制备成具有更薄的轮廓，并且具有更少的加工步骤，导致具有更高密度，更高可靠性和降低制造成本的装置。

公开(公告)号：US08405158B2

公开(公告)日：2013-03-26

申请号：US12832373

申请日：2010-07-08

申请人： Young-Bae Yoon ,  Jong-Hyuk Kim ,  Keonsoo Kim ,  Youngseop Rah ,  Yoonmoon Park

发明人： Young-Bae Yoon ,  Jong-Hyuk Kim ,  Keonsoo Kim ,  Youngseop Rah ,  Yoonmoon Park

IPC分类号： H01L27/088 ,  H01L29/76

CPC分类号： H01L27/11521 ,  G11C16/0483 ,  H01L27/11519

摘要： A semiconductor memory device and method of manufacturing the same, the device including string structures, the string structures including two or more adjacent string selection transistors connected in series to each other in a first direction and being spaced apart from one another in a second direction intersecting the first direction, the two or more string selection transistors having different threshold voltages; string selection lines, the string selection lines connecting the adjacent string selection transistors of the string structures in the second direction; and a bit line electrically connecting two or more adjacent string structures, wherein a device isolation layer between the adjacent string selection transistors in the second direction has recessed regions, and profiles of the recessed regions on respective sides of the string selection transistors are different from each other.

摘要翻译： 一种半导体存储器件及其制造方法，该器件包括串联结构，串联结构包括两个或多个相邻的串选择晶体管，它们在第一方向上彼此串联连接，并且在第二方向上相互间隔开 所述第一方向，所述两个或更多个串选择晶体管具有不同的阈值电压; 串选择线，串串选择线，连接串结构的相邻串选择晶体管沿第二方向; 以及电连接两个或更多个相邻串结构的位线，其中在第二方向上的相邻串选择晶体管之间的器件隔离层具有凹陷区域，并且串选择晶体管的相应侧上的凹陷区域的轮廓与每个不同 其他。

公开(公告)号：US20110038211A1

公开(公告)日：2011-02-17

申请号：US12832373

申请日：2010-07-08

申请人： Young-Bae Yoon ,  Jong-Hyuk Kim ,  Keonsoo Kim ,  Youngseop Rah ,  Yoonmoon Park

发明人： Young-Bae Yoon ,  Jong-Hyuk Kim ,  Keonsoo Kim ,  Youngseop Rah ,  Yoonmoon Park

IPC分类号： G11C16/04 ,  H01L27/088

CPC分类号： H01L27/11521 ,  G11C16/0483 ,  H01L27/11519

摘要： A semiconductor memory device and method of manufacturing the same, the device including string structures, the string structures including two or more adjacent string selection transistors connected in series to each other in a first direction and being spaced apart from one another in a second direction intersecting the first direction, the two or more string selection transistors having different threshold voltages; string selection lines, the string selection lines connecting the adjacent string selection transistors of the string structures in the second direction; and a bit line electrically connecting two or more adjacent string structures, wherein a device isolation layer between the adjacent string selection transistors in the second direction has recessed regions, and profiles of the recessed regions on respective sides of the string selection transistors are different from each other.

摘要翻译： 一种半导体存储器件及其制造方法，该器件包括串联结构，串联结构包括两个或更多个相邻的串选择晶体管，它们在第一方向上彼此串联连接并且沿第二方向相互间隔开 所述第一方向，所述两个或更多个串选择晶体管具有不同的阈值电压; 串选择线，串串选择线，连接串结构的相邻串选择晶体管沿第二方向; 以及电连接两个或更多个相邻串结构的位线，其中在第二方向上的相邻串选择晶体管之间的器件隔离层具有凹陷区域，并且串选择晶体管的相应侧上的凹陷区域的轮廓与每个不同 其他。

公开(公告)号：US20090315095A1

公开(公告)日：2009-12-24

申请号：US12456391

申请日：2009-06-16

申请人： Jonghyuk Kim ,  Han-Soo Kim ,  YoungSeop Rah ,  Min-sung Song ,  Jang Young Chul ,  Soon-Moon Jung ,  Wonseok Cho

发明人： Jonghyuk Kim ,  Han-Soo Kim ,  YoungSeop Rah ,  Min-sung Song ,  Jang Young Chul ,  Soon-Moon Jung ,  Wonseok Cho

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L21/82385 ,  H01L21/8221 ,  H01L21/823425 ,  H01L21/823456 ,  H01L21/823468 ,  H01L23/481 ,  H01L23/485 ,  H01L27/0688 ,  H01L27/11526 ,  H01L27/11551 ,  H01L2224/9202 ,  H01L21/76898

摘要： In multiple-layered memory devices, memory systems employing the same, and methods of forming such devices, a second memory device layer on a first memory device layer comprises a second substrate including a second memory cell region. The second substrate includes only a single well in the second memory cell region, the single well of the second memory cell region comprising a semiconducting material doped with impurity of one of a first type and second type. The single well defines an active region in the second memory cell region of the second substrate. Multiple second cell strings are arranged on the second substrate in the second active region. Although the second memory cell region includes only a single well, during a programming or erase operation of the memory cells of the second layer, requiring a high voltage to be applied to the single well in the substrate of the second layer, the high voltage will not interfere with the operation of the peripheral transistors of the first layer, second layer, or other layers, since they are isolated from each other. As a result, the substrate of the second layer can be prepared to have a thinner profile, and with fewer processing steps, resulting in devices with higher-density, greater reliability, and reduced fabrication costs.

摘要翻译： 在多层存储器件中，采用该器件的存储器系统和形成这种器件的方法在第一存储器件层上的第二存储器件层包括包括第二存储单元区域的第二衬底。 第二衬底仅包括第二存储单元区域中的单个阱，第二存储单元区域的单阱包括掺杂有第一类型和第二类型之一杂质的半导体材料。 单阱限定了第二衬底的第二存储单元区域中的有源区。 多个第二电池串被布置在第二有源区域中的第二衬底上。 虽然第二存储单元区域仅包括单个阱，但是在第二层的存储单元的编程或擦除操作期间，需要向第二层的衬底中的单个阱施加高电压，高电压将 不妨碍第一层，第二层或其它层的外围晶体管的操作，因为它们彼此隔离。 结果，第二层的基底可以被制备成具有更薄的轮廓，并且具有更少的加工步骤，导致具有更高密度，更高可靠性和降低制造成本的装置。