公开(公告)号：US20130038349A1

公开(公告)日：2013-02-14

申请号：US13570104

申请日：2012-08-08

申请人： Terng-Yin Hsu ,  Yuan-Te Liao ,  Kai-Shu Su

发明人： Terng-Yin Hsu ,  Yuan-Te Liao ,  Kai-Shu Su

IPC分类号： H03L7/00 ,  H03K19/20 ,  H03M1/12

CPC分类号： G06F1/08 ,  G04F5/10 ,  G04F10/005 ,  H03L7/0997

摘要： An all-digital clock generator includes a digitally-controlled clock generator and a processing unit. The digitally-controlled clock generator generates a clock signal in response to an enable signal and a digital signal. The processing unit has a frequency multiplier and a reference signal having a period, digitizes the period to generate a quantized signal, generates the digital signal according to the quantized signal and the frequency multiplier, and generates the enable signal according to the reference signal, the clock signal and the frequency multiplier.

摘要翻译： 全数字时钟发生器包括数字控制的时钟发生器和处理单元。 数字控制时钟发生器响应于使能信号和数字信号产生时钟信号。 处理单元具有倍频器和具有周期的参考信号，数字化周期以产生量化信号，根据量化信号和倍频器产生数字信号，并根据参考信号产生使能信号， 时钟信号和倍频器。

公开(公告)号：US08686756B2

公开(公告)日：2014-04-01

申请号：US13570104

申请日：2012-08-08

申请人： Terng-Yin Hsu ,  Yuan-Te Liao ,  Kai-Shu Su

发明人： Terng-Yin Hsu ,  Yuan-Te Liao ,  Kai-Shu Su

IPC分类号： H03K19/00 ,  H03K19/096 ,  H03K7/08 ,  H03L7/06

CPC分类号： G06F1/08 ,  G04F5/10 ,  G04F10/005 ,  H03L7/0997

摘要： An all-digital clock generator includes a digitally-controlled clock generator and a processing unit. The digitally-controlled clock generator generates a clock signal in response to an enable signal and a digital signal. The processing unit has a frequency multiplier and a reference signal having a period, digitizes the period to generate a quantized signal, generates the digital signal according to the quantized signal and the frequency multiplier, and generates the enable signal according to the reference signal, the clock signal and the frequency multiplier.

摘要翻译： 全数字时钟发生器包括数字控制的时钟发生器和处理单元。 数字控制时钟发生器响应于使能信号和数字信号产生时钟信号。 处理单元具有倍频器和具有周期的参考信号，数字化周期以产生量化信号，根据量化信号和倍频器产生数字信号，并根据参考信号产生使能信号， 时钟信号和倍频器。