公开(公告)号：US09806336B2

公开(公告)日：2017-10-31

申请号：US14429583

申请日：2012-09-21

申请人： Tatsuya Hashimoto ,  Yusuke Fukumoto ,  Keisuke Ohara ,  Yuji Yokoyama

发明人： Tatsuya Hashimoto ,  Yusuke Fukumoto ,  Keisuke Ohara ,  Yuji Yokoyama

IPC分类号： H01M4/36 ,  H01M10/05 ,  H01M4/13 ,  H01M4/139 ,  H01M2/34 ,  H01M10/0525 ,  H01M4/02

CPC分类号： H01M4/366 ,  H01M2/345 ,  H01M4/13 ,  H01M4/139 ,  H01M10/05 ,  H01M10/0525 ,  H01M2004/021 ,  H01M2004/028

摘要： Provided is a positive electrode for nonaqueous electrolyte secondary batteries including a positive electrode mixture layer formed of a positive electrode mixture paste containing a positive electrode active material. The positive electrode active material has a particle diameter of 2 μm or more and less than 7 μm. The positive electrode mixture layer includes a first mixture layer in which a maximum diameter of pores formed between particles of the positive electrode active material is more than 1.0 μm and 5.0 μm or less, and a second mixture layer in which a maximum diameter of the pores is 1.0 μm or less. The second mixture layer is arranged closer to the current collector than the first mixture layer. A ratio of a thickness of the first mixture layer to a thickness of the second mixture layer is more than 0.1 and 1.0 or less.

公开(公告)号：US20150255786A1

公开(公告)日：2015-09-10

申请号：US14429583

申请日：2012-09-21

申请人： Tatsuya HASHIMOTO ,  Yusuke FUKUMOTO ,  Keisuke OHARA ,  Yuji YOKOYAMA

发明人： Tatsuya Hashimoto ,  Yusuke Fukumoto ,  Keisuke Ohara ,  Yuji Yokoyama

IPC分类号： H01M4/36 ,  H01M10/05

CPC分类号： H01M4/366 ,  H01M2/345 ,  H01M4/13 ,  H01M4/139 ,  H01M10/05 ,  H01M10/0525 ,  H01M2004/021 ,  H01M2004/028

摘要： Provided is a positive electrode for nonaqueous electrolyte secondary batteries including a positive electrode mixture layer formed of a positive electrode mixture paste containing a positive electrode active material. The positive electrode active material has a particle diameter of 2 μm or more and less than 7 μm. The positive electrode mixture layer includes a first mixture layer in which a maximum diameter of pores formed between particles of the positive electrode active material is more than 1.0 μm and 5.0 μm or less, and a second mixture layer in which a maximum diameter of the pores is 1.0 μm or less. The second mixture layer is arranged closer to the current collector than the first mixture layer. A ratio of a thickness of the first mixture layer to a thickness of the second mixture layer is more than 0.1 and 1.0 or less.

摘要翻译： 本发明提供一种非水电解质二次电池用正极，其包括由含有正极活性物质的正极混合物糊形成的正极合剂层。 正极活性物质的粒径为2μm以上且小于7μm。 正极复合层包括第一混合层，其中在正极活性物质的颗粒之间形成的孔的最大直径大于1.0μm和5.0μm以下，第二混合层，其中孔的最大直径 为1.0μm以下。 第二混合物层比第一混合物层更靠近集电体布置。 第一混合物层的厚度与第二混合物层的厚度的比例大于0.1和1.0以下。

公开(公告)号：US20150221951A1

公开(公告)日：2015-08-06

申请号：US14426799

申请日：2012-09-10

申请人： Tatsuya Hashimoto ,  Keisuke Ohara ,  Yuji Yokoyama ,  Yusuke Fukumoto

发明人： Tatsuya Hashimoto ,  Keisuke Ohara ,  Yuji Yokoyama ,  Yusuke Fukumoto

IPC分类号： H01M4/62 ,  H01M10/052

CPC分类号： H01M4/62 ,  H01M4/13 ,  H01M4/139 ,  H01M4/621 ,  H01M4/622 ,  H01M10/052 ,  H01M2220/20 ,  Y02E60/122 ,  Y02T10/7011

摘要： This invention provides a lithium secondary battery that comprises a positive electrode comprising a positive electrode active material layer and a negative electrode comprising a negative electrode active material layer. The positive electrode active material layer and the negative electrode active material layer are placed to face each other. The negative electrode active material layer has an area A comprising a non-positive-electrode-facing portion that does not face the positive electrode active material layer. The area A comprises a negative electrode active material, a hot-melt binder and a temperature-sensitive thickener. The hot-melt binder has a melting point and the temperature-sensitive thickener has a gelation temperature both in a range of 45° C. to 100° C.

摘要翻译： 本发明提供一种锂二次电池，其包括正极，其包括正极活性物质层和包含负极活性物质层的负极。 将正极活性物质层和负极活性物质层配置成彼此相对。 负极活性物质层具有包含不与正极活性物质层相对的非正极对向部的区域A. 区域A包括负极活性材料，热熔粘合剂和温度敏感增稠剂。 热熔粘合剂具有熔点，并且温度敏感性增稠剂的凝胶化温度均在45℃至100℃的范围内。

公开(公告)号：US20130309529A1

公开(公告)日：2013-11-21

申请号：US13981849

申请日：2012-01-12

申请人： Yuji Yokoyama ,  Yasushi Nakagiri

发明人： Yuji Yokoyama ,  Yasushi Nakagiri

IPC分类号： H01M10/52

CPC分类号： H01M10/52 ,  H01M2/022 ,  H01M2/0413 ,  H01M2/1241 ,  H01M10/0525

摘要： Disclosed is a cylindrical battery including: a cylindrical wound electrode group including sheet-like positive and negative electrodes, and a separator interposed therebetween; a bottomed cylindrical battery case having an opening and accommodating the electrode group; and a sealing unit sealing the opening. The electrode group has, at its center portion, a cavity extending in the axis direction thereof. The sealing unit includes a terminal plate having a vent hole, and a valve plate made of an electrically conductive material. The valve plate includes first and second rupturable portions each configured to be ruptured by an increase in the internal pressure of the battery case. The first rupturable portion is provided so as to surround a first region of the valve plate facing the cavity. The second rupturable portion is provided so as to surround a second region of the valve plate. The second region includes the first region.

摘要翻译： 公开了一种圆柱形电池，包括：包括片状正极和负极的圆柱形卷绕电极组和插入其间的隔膜; 具有开口并容纳电极组的有底圆柱形电池盒; 以及密封单元密封开口。 电极组在其中心部分具有沿其轴向延伸的空腔。 密封单元包括具有通气孔的端子板和由导电材料制成的阀板。 阀板包括第一和第二可破裂部分，每个可破裂部分被构造成通过电池壳体的内部压力的增加而破裂。 第一可破裂部分设置成围绕面对空腔的阀板的第一区域。 第二可破裂部分设置成围绕阀板的第二区域。 第二个地区包括第一个地区。

公开(公告)号：US08093931B2

公开(公告)日：2012-01-10

申请号：US12420253

申请日：2009-04-08

申请人： Toshio Shinomiya ,  Akio Koyama ,  Yuji Yokoyama

发明人： Toshio Shinomiya ,  Akio Koyama ,  Yuji Yokoyama

IPC分类号： H03L7/00

CPC分类号： H03K17/223 ,  G06F1/24

摘要： In a semiconductor integrated circuit device generating internal power from external power, an abnormal operation may occur due to an indefinite state of a control signal when the external power is applied and the internal power rises. The semiconductor integrated circuit includes an internal power generating circuit, a control circuit receiving internal power and supplying a first control signal, and a power-on reset circuit generating a reset signal at rising of the internal power. When internal power rises, the reset signal masks an indefinite state of the first control signal supplied from the control circuit.

摘要翻译： 在从外部电力产生内部电力的半导体集成电路装置中，当施加外部电力并且内部电力上升时，可能由于控制信号的不确定状态而发生异常操作。 半导体集成电路包括内部发电电路，接收内部电力并提供第一控制信号的控制电路，以及在内部电力上升时产生复位信号的上电复位电路。 当内部电源上升时，复位信号屏蔽从控制电路提供的第一控制信号的不确定状态。

公开(公告)号：US20090268360A1

公开(公告)日：2009-10-29

申请号：US12428627

申请日：2009-04-23

申请人： Toshio SHINOMIYA ,  Yuji YOKOYAMA ,  Akihiro NAGATANI ,  Masato KITA

发明人： Toshio SHINOMIYA ,  Yuji YOKOYAMA ,  Akihiro NAGATANI ,  Masato KITA

IPC分类号： H02H9/04

CPC分类号： H02H9/046

摘要： In a protection circuit for protecting semiconductor integrated circuit devices from an electrostatic breakdown or a latch-up due to an external surge, etc, a drain terminal of a PMOS transistor MP1, having a source terminal connected to a power supply VDD and a gate terminal receiving a control signal VG1 which a control circuit 2 generates on the basis of a power supply GND, is connected to one end of a resistor R1, having the other end connected to the power supply GND, and to a gate terminal of an NMOS transistor MN1 having a drain terminal and a source terminal connected to the power supply VDD and the power supply GND, respectively, and outputs an internal signal VG2 to the gate terminal of the NMOS transistor. When a predetermined voltage or more is applied to the power supply, the power supply is short-circuited.

摘要翻译： 在用于保护半导体集成电路器件免受外部浪涌等的静电击穿或闩锁的保护电路中，PMOS晶体管MP1的漏极端子具有连接到电源VDD和栅极端子的源极端子 接收控制电路2基于电源GND产生的控制信号VG1连接到另一端连接到电源GND的电阻器R1的一端，并连接到NMOS晶体管的栅极端子 MN1具有漏极端子和源极端子，分别连接到电源VDD和电源GND，并将内部信号VG2输出到NMOS晶体管的栅极端子。 当对电源施加预定电压以上时，电源短路。

公开(公告)号：US07151025B2

公开(公告)日：2006-12-19

申请号：US10388447

申请日：2003-03-17

申请人： Kazuo Itabashi ,  Osamu Tsuboi ,  Yuji Yokoyama ,  Kenichi Inoue ,  Koichi Hashimoto ,  Wataru Futo

发明人： Kazuo Itabashi ,  Osamu Tsuboi ,  Yuji Yokoyama ,  Kenichi Inoue ,  Koichi Hashimoto ,  Wataru Futo

IPC分类号： H01O21/8242

CPC分类号： H01L27/10852 ,  H01L21/76897 ,  H01L27/105 ,  H01L27/10805 ,  H01L27/10817 ,  H01L28/91

摘要： A method of manufacturing a semiconductor device on a semiconductor substrate having a first region and a second region. This method beings by forming a transistor in the first region of said semiconductor substrate. This transistor includes a pair of impurity diffusion regions and a gate electrode. Then forming a first insulating film over the first and second regions with this first insulating film covering the transistor in the first region. Thereafter, patterning the first insulating film to selectively remove the first insulating film in the second region. Then forming a second insulating film over the first and second regions. Thereafter, forming at least one contact hole through the second and first insulating film. The contact hole reaches one of the impurity diffusion regions. Finally, forming a conductive layer in the contact hole.

摘要翻译： 一种在具有第一区域和第二区域的半导体衬底上制造半导体器件的方法。 该方法通过在所述半导体衬底的第一区域中形成晶体管来实现。 该晶体管包括一对杂质扩散区和栅电极。 然后在第一和第二区域上形成第一绝缘膜，该第一绝缘膜覆盖第一区域中的晶体管。 此后，图案化第一绝缘膜以选择性地去除第二区域中的第一绝缘膜。 然后在第一和第二区域上形成第二绝缘膜。 此后，通过第二和第一绝缘膜形成至少一个接触孔。 接触孔到达杂质扩散区域中的一个。 最后，在接触孔中形成导电层。

公开(公告)号：US5777952A

公开(公告)日：1998-07-07

申请号：US678267

申请日：1996-07-11

申请人： Hajime Nishimura ,  Atsushi Ichikawa ,  Akio Yabe ,  Yuji Yokoyama

发明人： Hajime Nishimura ,  Atsushi Ichikawa ,  Akio Yabe ,  Yuji Yokoyama

IPC分类号： G11B11/10 ,  G11B11/105 ,  G11B11/00

CPC分类号： G11B11/10558 ,  G11B11/1056

摘要： A bias magnet unit has a permanent magnet that applies a bias magnetic field to an optical spot on a magneto-optical disk. A driving coil rotates the magnet in order to change a polarity of the bias magnetic field. A sensor detects the intensity and polarity of the bias magnetic field to confirm the rotational position of the magnet after it has been rotated. A linkage structure that is connected between a magnet holder of the magnet unit and the housing has arms that drive the magnet unit between two positions, one in which the magneto-optical disk cartridge can be inserted into the device and another in which the disk is loaded onto the spindle motor for recording/playback. Overall, the components of the device cooperate structurally to provide a relatively thin device structure having low power consumption.

摘要翻译： 偏置磁体单元具有向磁光盘上的光点施加偏置磁场的永磁体。 驱动线圈使磁体旋转，以改变偏磁场的极性。 传感器检测偏磁场的强度和极性，以确认磁体旋转后的旋转位置。 连接在磁体单元的磁体保持器和壳体之间的连接结构具有在两个位置之间驱动磁体单元的臂，其中可以将磁光盘盒插入到该装置中，其中磁盘 加载到主轴电机上进行记录/播放。 总体而言，该装置的部件在结构上配合以提供具有低功耗的较薄的装置结构。

公开(公告)号：US5619455A

公开(公告)日：1997-04-08

申请号：US35651

申请日：1993-03-23

申请人： Noboru Akiyama ,  Yuji Yokoyama ,  Tatsuyuki Ohta ,  Kunihiko Suzuki ,  Yutaka Kobayashi

发明人： Noboru Akiyama ,  Yuji Yokoyama ,  Tatsuyuki Ohta ,  Kunihiko Suzuki ,  Yutaka Kobayashi

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C11/401 ,  G11C29/00 ,  G11C29/34 ,  G11C7/00

CPC分类号： G11C7/1039

摘要： A pipeline-operating type memory system is arranged to have a first input unit for receiving a selector address signal for selecting data; a second input unit for receiving at least an address strobe signal, an X address signal and a Y address signal for selecting data; a first unit for receiving the X address signal and the Y address signal, latching these signals utilizing a first clock signal, and continuously outputting at least either of the X and the Y address signals until these address signals are unlatched; and a second unit for latching a selector address data signal output from the first input unit utilizing the first clock signal, and continuously and selectively outputting at least either of the address signal until the signal is unlatched. The memory system operates to transfer data in a manner to suit the pipeline operating cycle at a normal operating mode and at a fast page mode.

摘要翻译： 流水线操作型存储器系统被布置成具有用于接收用于选择数据的选择器地址信号的第一输入单元; 第二输入单元，用于至少接收地址选通信号，X地址信号和Y地址信号，用于选择数据; 用于接收X地址信号和Y地址信号的第一单元，利用第一时钟信号锁存这些信号，并且连续地输出X和Y地址信号中的至少一个，直到这些地址信号被解锁为止; 以及第二单元，用于使用所述第一时钟信号来锁存从所述第一输入单元输出的选择器地址数据信号，并且连续且选择性地输出所述地址信号中的至少一个，直到所述信号被解锁为止。 存储器系统操作以在正常操作模式和快速页模式下以适合流水线操作周期的方式传送数据。

公开(公告)号：US5398318A

公开(公告)日：1995-03-14

申请号：US608370

申请日：1990-11-02

申请人： Atsushi Hiraishi ,  Takashi Akioka ,  Yutaka Kobayashi ,  Yuji Yokoyama ,  Masahiro Iwamura ,  Tatsumi Yamauchi ,  Shigeru Takahashi ,  Hideaki Uchida ,  Akira Ide

发明人： Atsushi Hiraishi ,  Takashi Akioka ,  Yutaka Kobayashi ,  Yuji Yokoyama ,  Masahiro Iwamura ,  Tatsumi Yamauchi ,  Shigeru Takahashi ,  Hideaki Uchida ,  Akira Ide

IPC分类号： G11C11/417 ,  G11C11/409 ,  H03K17/16 ,  H03K17/687 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/0185 ,  H03K19/08 ,  H03K19/088 ,  H03K19/0944 ,  G06F13/00

CPC分类号： H03K19/09448 ,  H03K17/164 ,  H03K19/00361

摘要： An improved buffer circuit arrangement is provided which is particularly useful for semiconductor integrated circuit semiconductor memories and microprocessors. The buffer circuit is capable of switching large loads in various types of LSIs, and features a low noise and high speed circuit operation. This is accomplished by a parallel connection of output transistors in an output buffer circuit, and by differentiating the starting time of operation between the output transistors connected in parallel without using a delay circuit. For example, differentiating the starting times can be achieved by either providing the transistors with different characteristics from one another or the driving circuits with different characteristics from one another. Another aspect of the circuit is the provision of a two-level preset arrangement which presets the output node of the circuit to predetermined values before the input signals are applied.

摘要翻译： 提供了一种改进的缓冲电路装置，其特别适用于半导体集成电路半导体存储器和微处理器。 缓冲电路能够切换各种类型的LSI中的大负载，并且具有低噪声和高速电路操作。 这通过输出缓冲器电路中的输出晶体管的并联连接，并且通过区分并联连接的输出晶体管之间的操作的起始时间而不使用延迟电路来实现。 例如，通过提供具有彼此不同特性的晶体管或具有彼此不同特性的驱动电路，可以实现区分起始时间。 电路的另一方面是提供两级预置布置，其在施加输入信号之前将电路的输出节点预设为预定值。