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    Semiconductor process
    1.
    发明授权
    Semiconductor process 有权
    半导体工艺

    公开(公告)号：US08674433B2

    公开(公告)日：2014-03-18

    申请号：US13216259

    申请日：2011-08-24

    申请人： Chin-I Liao ,  Chia-Lin Hsu ,  Ming-Yen Li ,  Hsin-Huei Wu ,  Yung-Lun Hsieh ,  Chien-Hao Chen ,  Bo-Syuan Lee

    发明人： Chin-I Liao ,  Chia-Lin Hsu ,  Ming-Yen Li ,  Hsin-Huei Wu ,  Yung-Lun Hsieh ,  Chien-Hao Chen ,  Bo-Syuan Lee

    IPC分类号： H01L29/66

    CPC分类号： H01L29/66795 ,  H01L29/66628

    摘要： A semiconductor process includes the following steps. A substrate is provided. At least a fin-shaped structure is formed on the substrate. An oxide layer is formed on the substrate without the fin-shaped structure being formed thereon. A gate is formed to cover a part of the oxide layer and a part of the fin-shaped structure. An etching process is performed to etch a part of the fin-shaped structure beside the gate, therefore at least a recess is formed in the fin-shaped structure. An epitaxial process is performed to form an epitaxial layer in the recess, wherein the epitaxial layer has a hexagon-shaped profile structure.

    摘要翻译： 半导体工艺包括以下步骤。 提供基板。 在基板上形成至少一个鳍状结构。 在基板上形成氧化层，而不形成鳍状结构。 形成栅极以覆盖氧化物层的一部分和鳍状结构的一部分。 进行蚀刻处理以蚀刻栅极旁边的鳍状结构的一部分，因此在鳍状结构中至少形成凹部。 执行外延工艺以在凹部中形成外延层，其中外延层具有六边形轮廓结构。

    METHOD FOR MANUFACTURING THROUGH-SILICON VIA
    5.
    发明申请
    METHOD FOR MANUFACTURING THROUGH-SILICON VIA 有权
    通过硅制造方法

    公开(公告)号：US20130011938A1

    公开(公告)日：2013-01-10

    申请号：US13176790

    申请日：2011-07-06

    申请人： Wei-Che TSAO ,  Chia-Lin Hsu ,  Jen-Chieh Lin ,  Teng-Chun Tsai ,  Hsin-Kuo Hsu ,  Ya-Hsueh Hsieh ,  Ren-Peng Huang ,  Chih-Hsien Chen ,  Wen-Chin Lin ,  Yung-Lun Hsieh

    发明人： Wei-Che TSAO ,  Chia-Lin Hsu ,  Jen-Chieh Lin ,  Teng-Chun Tsai ,  Hsin-Kuo Hsu ,  Ya-Hsueh Hsieh ,  Ren-Peng Huang ,  Chih-Hsien Chen ,  Wen-Chin Lin ,  Yung-Lun Hsieh

    IPC分类号： H01L21/66 ,  H01L21/306 ,  H01L21/304

    CPC分类号： H01L21/31053 ,  H01L21/3212 ,  H01L21/76898 ,  H01L22/12 ,  H01L22/26 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for manufacturing TSVs, wherein the method comprises several steps as follows: A stack structure having a substrate and an ILD layer (inter layer dielectric layer) is provided, in which an opening penetrating through the ILD layer and further extending into the substrate is formed. After an insulator layer and a metal barrier layer are formed on the stack structure and the sidewalls of the opening, a top metal layer is then formed on the stack structure to fulfill the opening. A first planarization process stopping on the barrier layer is conducted to remove a portion of the top metal layer. A second planarization process stopping on the ILD layer is subsequently conducted to remove a portion of the metal barrier layer, a portion of the insulator layer and a portion of the top metal layer, wherein the second planarization process has a polishing endpoint determined by a light interferometry or a motor current.

    摘要翻译： 一种制造TSV的方法，其中该方法包括以下几个步骤：提供具有基板和ILD层（层间电介质层）的堆叠结构，其中穿透ILD层并进一步延伸到基板中的开口是 形成。 在堆叠结构和开口的侧壁上形成绝缘体层和金属阻挡层之后，在堆叠结构上形成顶部金属层以实现开口。 进行停止在阻挡层上的第一平面化处理以去除顶部金属层的一部分。 随后进行停止在ILD层上的第二平坦化处理以去除金属阻挡层的一部分，绝缘体层的一部分和顶部金属层的一部分，其中第二平坦化工艺具有由光线确定的抛光终点 干涉测量或电机电流。

    Multi-gate field-effect transistor and process thereof
    6.
    发明授权
    Multi-gate field-effect transistor and process thereof 有权
    多栅极场效应晶体管及其工艺

    公开(公告)号：US08796695B2

    公开(公告)日：2014-08-05

    申请号：US13530127

    申请日：2012-06-22

    申请人： Chin-I Liao ,  Chia-Lin Hsu ,  Ming-Yen Li ,  Yung-Lun Hsieh ,  Chien-Hao Chen ,  Bo-Syuan Lee

    发明人： Chin-I Liao ,  Chia-Lin Hsu ,  Ming-Yen Li ,  Yung-Lun Hsieh ,  Chien-Hao Chen ,  Bo-Syuan Lee

    IPC分类号： H01L29/772

    CPC分类号： H01L29/66795 ,  H01L29/1054 ,  H01L29/66484 ,  H01L29/785

    摘要： A Multi-Gate Field-Effect Transistor includes a fin-shaped structure, a gate structure, at least an epitaxial structure and a gradient cap layer. The fin-shaped structure is located on a substrate. The gate structure is disposed across a part of the fin-shaped structure and the substrate. The epitaxial structure is located on the fin-shaped structure beside the gate structure. The gradient cap layer is located on each of the epitaxial structures. The gradient cap layer is a compound semiconductor, and the concentration of one of the ingredients of the compound semiconductor has a gradient distribution decreasing from bottom to top. Moreover, the present invention also provides a Multi-Gate Field-Effect Transistor process forming said Multi-Gate Field-Effect Transistor.

    摘要翻译： 多栅极场效应晶体管包括鳍状结构，栅极结构，至少外延结构和梯度盖层。 鳍状结构位于基板上。 栅极结构设置在鳍状结构和衬底的一部分上。 外延结构位于栅极结构旁边的鳍状结构上。 梯度盖层位于每个外延结构上。 梯度盖层是化合物半导体，化合物半导体的成分之一的浓度具有从下到上减小的梯度分布。 此外，本发明还提供一种形成所述多栅极场效应晶体管的多栅极场效应晶体管工艺。

    MULTI-GATE FIELD-EFFECT TRANSISTOR AND PROCESS THEREOF
    9.
    发明申请
    MULTI-GATE FIELD-EFFECT TRANSISTOR AND PROCESS THEREOF 有权
    多栅极场效应晶体管及其工艺

    公开(公告)号：US20130341638A1

    公开(公告)日：2013-12-26

    申请号：US13530127

    申请日：2012-06-22

    申请人： Chin-I Liao ,  Chia-Lin Hsu ,  Ming-Yen Li ,  Yung-Lun Hsieh ,  Chien-Hao Chen ,  Bo-Syuan Lee

    发明人： Chin-I Liao ,  Chia-Lin Hsu ,  Ming-Yen Li ,  Yung-Lun Hsieh ,  Chien-Hao Chen ,  Bo-Syuan Lee

    IPC分类号： H01L29/772 ,  H01L21/20 ,  H01L29/161

    CPC分类号： H01L29/66795 ,  H01L29/1054 ,  H01L29/66484 ,  H01L29/785

    摘要： A Multi-Gate Field-Effect Transistor includes a fin-shaped structure, a gate structure, at least an epitaxial structure and a gradient cap layer. The fin-shaped structure is located on a substrate. The gate structure is disposed across a part of the fin-shaped structure and the substrate. The epitaxial structure is located on the fin-shaped structure beside the gate structure. The gradient cap layer is located on each of the epitaxial structures. The gradient cap layer is a compound semiconductor, and the concentration of one of the ingredients of the compound semiconductor has a gradient distribution decreasing from bottom to top. Moreover, the present invention also provides a Multi-Gate Field-Effect Transistor process forming said Multi-Gate Field-Effect Transistor.

    摘要翻译： 多栅极场效应晶体管包括鳍状结构，栅极结构，至少外延结构和梯度盖层。 鳍状结构位于基板上。 栅极结构设置在鳍状结构和衬底的一部分上。 外延结构位于栅极结构旁边的鳍状结构上。 梯度盖层位于每个外延结构上。 梯度盖层是化合物半导体，化合物半导体的成分之一的浓度具有从下到上减小的梯度分布。 此外，本发明还提供一种形成所述多栅极场效应晶体管的多栅极场效应晶体管工艺。

    SEMICONDUCTOR PROCESS
    10.
    发明申请
    SEMICONDUCTOR PROCESS 有权
    半导体工艺

    公开(公告)号：US20130052778A1

    公开(公告)日：2013-02-28

    申请号：US13216259

    申请日：2011-08-24

    申请人： Chin-I Liao ,  Chia-Lin Hsu ,  Ming-Yen Li ,  Hsin-Huei Wu ,  Yung-Lun Hsieh ,  Chien-Hao Chen ,  Bo-Syuan Lee

    发明人： Chin-I Liao ,  Chia-Lin Hsu ,  Ming-Yen Li ,  Hsin-Huei Wu ,  Yung-Lun Hsieh ,  Chien-Hao Chen ,  Bo-Syuan Lee

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66795 ,  H01L29/66628

    摘要： A semiconductor process includes the following steps. A substrate is provided. At least a fin-shaped structure is formed on the substrate. An oxide layer is formed on the substrate without the fin-shaped structure being formed thereon. A gate is formed to cover a part of the oxide layer and a part of the fin-shaped structure. An etching process is performed to etch a part of the fin-shaped structure beside the gate, therefore at least a recess is formed in the fin-shaped structure. An epitaxial process is performed to form an epitaxial layer in the recess, wherein the epitaxial layer has a hexagon-shaped profile structure.

    摘要翻译： 半导体工艺包括以下步骤。 提供基板。 在基板上形成至少一个鳍状结构。 在基板上形成氧化层，而不形成鳍状结构。 形成栅极以覆盖氧化物层的一部分和鳍状结构的一部分。 进行蚀刻处理以蚀刻栅极旁边的鳍状结构的一部分，因此在鳍状结构中至少形成凹部。 执行外延工艺以在凹部中形成外延层，其中外延层具有六边形轮廓结构。