公开(公告)号：US09722818B2

公开(公告)日：2017-08-01

申请号：US14492237

申请日：2014-09-22

申请人： Ming-Chieh Huang ,  Chan-Hong Chern ,  Tao Wen Chung ,  Yuwen Swei ,  Chih-Chang Lin ,  Tsung-Ching Huang

发明人： Ming-Chieh Huang ,  Chan-Hong Chern ,  Tao Wen Chung ,  Yuwen Swei ,  Chih-Chang Lin ,  Tsung-Ching Huang

IPC分类号： H03H7/30 ,  H03H7/40 ,  H03K5/159 ,  H04L25/03 ,  H04L25/06 ,  H04L25/08

CPC分类号： H04L25/03057 ,  H04L25/06 ,  H04L25/08

摘要： A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit.

公开(公告)号：US08971395B2

公开(公告)日：2015-03-03

申请号：US13293513

申请日：2011-11-10

申请人： Ming-Chieh Huang ,  Jing Jing Chen ,  Chan-Hong Chern ,  Tao Wen Chung ,  Chih-Chang Lin ,  Yuwen Swei

发明人： Ming-Chieh Huang ,  Jing Jing Chen ,  Chan-Hong Chern ,  Tao Wen Chung ,  Chih-Chang Lin ,  Yuwen Swei

IPC分类号： H03H7/30 ,  H04L25/03

CPC分类号： H04L25/03057 ,  H04L2025/0349 ,  H04L2025/03566 ,  H04L2025/03617 ,  H04L2025/03687

摘要： A Decision Feedback Equalizer (DFE) with programmable taps includes a summer configured to receive a DFE input signal. Delay elements are coupled to the summer. The delay elements are connected in series. Each delay element provides a respective delayed signal of an input signal to the delay element. A weight generator is configured to provide tap weights. The DFE is configured to multiply each tap weight to the respective delayed signal from the respective delay element to provide tap outputs. Each tap output is selectively enabled to be added to the summer or disabled based on a first comparison of a first threshold value and each impulse response or each tap weight corresponding to the respective tap output, where the impulse response is the DFE input signal in response to a pulse signal transmitted through a channel.

摘要翻译： 具有可编程抽头的判决反馈均衡器（DFE）包括一个加法器，用于接收DFE输入信号。 延迟元素与夏天相结合。 延迟元件串联连接。 每个延迟元件向延迟元件提供输入信号的相应延迟信号。 重量发生器被配置成提供抽头重量。 DFE被配置为将每个抽头权重乘以来自相应延迟元件的相应延迟信号以提供抽头输出。 基于第一阈值和对应于各抽头输出的每个脉冲响应或每个抽头权重的第一比较，每个抽头输出被选择性地被加到加法器或禁止中，其中脉冲响应是响应中的DFE输入信号 通过通道传输的脉冲信号。

公开(公告)号：US08698566B2

公开(公告)日：2014-04-15

申请号：US13252498

申请日：2011-10-04

申请人： Chan-Hong Chern ,  Ming-Chieh Huang ,  Tao Wen Chung ,  Chih-Chang Lin ,  Fu-Lung Hsueh ,  Yuwen Swei

发明人： Chan-Hong Chern ,  Ming-Chieh Huang ,  Tao Wen Chung ,  Chih-Chang Lin ,  Fu-Lung Hsueh ,  Yuwen Swei

IPC分类号： H03L7/085 ,  H03L7/10 ,  H03B5/12

CPC分类号： H03L7/102 ,  H03L7/099 ,  H03L2207/06

摘要： An inductor-capacitor phase locked loop (LCPLL) includes an inductor-capacitor voltage controlled oscillator (LCVCO) that provides an output frequency. A calibration circuit includes two comparators and provides a coarse tune signal to the LCVCO. The two comparators respectively compare the loop filter signal with a first reference voltage and a second reference voltage that is higher than the first reference voltage to supply a first and second comparator output, respectively. The calibration circuit is capable of adjusting the coarse tune signal continuously in voltage values and adjusts the coarse tune signal based on the two comparator outputs. A loop filter provides a loop filter signal to the calibration circuit and a fine tune signal to the LCVCO. A coarse tune frequency range is greater than a fine tune frequency range.

摘要翻译： 电感 - 电容器锁相环（LCPLL）包括提供输出频率的电感 - 电容压控振荡器（LCVCO）。 校准电路包括两个比较器，并向LCVCO提供粗调信号。 两个比较器分别将环路滤波器信号与第一参考电压和高于第一参考电压的第二参考电压进行比较，以分别提供第一和第二比较器输出。 校准电路能够在电压值中连续调整粗调信号，并根据两个比较器输出调整粗调信号。 环路滤波器向校准电路提供环路滤波器信号，并向LCVCO提供微调信号。 粗调频率范围大于微调频率范围。

公开(公告)号：US20130120884A1

公开(公告)日：2013-05-16

申请号：US13293853

申请日：2011-11-10

申请人： Tao Wen Chung ,  Chan-Hong Chern ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Yuwen Swei

发明人： Tao Wen Chung ,  Chan-Hong Chern ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Yuwen Swei

IPC分类号： H02H9/04

CPC分类号： H02H9/04 ,  H01L23/60 ,  H01L27/0248 ,  H01L2924/0002 ,  H03F2200/294 ,  H03F2203/45638 ,  H03G1/0023 ,  H03K3/35613 ,  H03K19/018514 ,  H01L2924/00

摘要： An input/output (I/O) circuit includes an electrostatic discharge (ESD) protection circuit electrically coupled with an output node of the I/O circuit. At least one inductor and at least one loading are electrically coupled in a series fashion and between the output node of the I/O circuit and a power line. A circuitry is electrically coupled with a node between the at least one inductor and the at least one loading. The circuitry is operable to increase a current flowing through the at least one inductor during a signal transition.

摘要翻译： 输入/输出（I / O）电路包括与I / O电路的输出节点电耦合的静电放电（ESD）保护电路。 至少一个电感器和至少一个负载以串联方式电耦合，并且在I / O电路的输出节点和电力线之间。 电路与所述至少一个电感器和所述至少一个负载之间的节点电耦合。 电路可操作以在信号转换期间增加流过至少一个电感器的电流。

公开(公告)号：US08432204B1

公开(公告)日：2013-04-30

申请号：US13344637

申请日：2012-01-06

申请人： Chan-Hong Chern ,  Ming-Chieh Huang ,  Tao Wen Chung ,  Chih-Chang Lin ,  Yuwen Swei ,  Fu-Lung Hsueh

发明人： Chan-Hong Chern ,  Ming-Chieh Huang ,  Tao Wen Chung ,  Chih-Chang Lin ,  Yuwen Swei ,  Fu-Lung Hsueh

IPC分类号： H03L7/06

CPC分类号： H03L7/102 ,  H03L7/099 ,  H03L7/104

摘要： A PLL circuit includes a phase frequency detector; a programmable charge pump coupled to an output of the phase frequency detector; a loop filter coupled to an output of the charge pump, the loop filter providing a fine tuning voltage; a first voltage-to-current converter, the first voltage-to-current converter providing a fine tuning current corresponding to the fine tuning voltage; a current-controlled oscillator (CCO); a feedback divider coupled to an output of the CCO and an input of the phase frequency detector; and an analog calibration circuit. The analog calibration circuit provides a coarse adjustment current for coarse adjustments to a frequency pivot point for an oscillator frequency of the CCO, wherein the CCO generates a frequency signal at an output responsive to a summed coarse adjustment and fine tuning current, wherein the frequency pivot point is continuously adjustable.

摘要翻译： PLL电路包括相位检波器; 耦合到所述相位频率检测器的输出的可编程电荷泵; 耦合到电荷泵的输出的环路滤波器，所述环路滤波器提供微调电压; 第一电压 - 电流转换器，第一电压 - 电流转换器提供对应于微调电压的微调电流; 电流控制振荡器（CCO）; 耦合到CCO的输出的反馈分压器和相位频率检测器的输入端; 和模拟校准电路。 模拟校准电路提供用于对CCO的振荡器频率的频率枢转点进行粗调整的粗调电流，其中CCO响应于总和的粗调和微调电流而在输出端产生频率信号，其中频率枢轴 点连续可调。

公开(公告)号：US08378654B2

公开(公告)日：2013-02-19

申请号：US12750260

申请日：2010-03-30

申请人： Chan-Hong Chern ,  Tzu Ching Chang ,  Min-Shueh Yuan ,  Yuwen Swei ,  Chih-Chang Lin ,  Chiang Pu ,  Ming-Chieh Huang ,  Kuoyuan Hsu

发明人： Chan-Hong Chern ,  Tzu Ching Chang ,  Min-Shueh Yuan ,  Yuwen Swei ,  Chih-Chang Lin ,  Chiang Pu ,  Ming-Chieh Huang ,  Kuoyuan Hsu

IPC分类号： G05F1/44

CPC分类号： H02M3/158 ,  G05F1/44 ,  G05F1/56

摘要： A voltage regulator circuit with high accuracy and Power Supply Rejection Ratio (PSRR) is provided. In one embodiment, an op-amp with a voltage reference input to an inverting input has the first output connected to a PMOS transistor's gate. The PMOS transistor's source and drain are each connected to the power supply and the voltage regulator output. The voltage regulator output is connected to an NMOS transistor biased in saturation mode and a series of two resistors. The non-inverting input of the op-amp is connected in between the two resistors for the first feedback loop. The op-amp's second output is connected to the gate of the NMOS transistor through an AC-coupling capacitor for the second feedback loop. The op-amp's first output can be connected to the power supply voltage through a capacitor to further improve high frequency PSRR. In another embodiment, the role of PMOS and NMOS transistors is reversed.

摘要翻译： 提供了具有高精度和电源抑制比（PSRR）的稳压电路。 在一个实施例中，具有到反相输入的电压参考输入的运算放大器具有连接到PMOS晶体管的栅极的第一输出。 PMOS晶体管的源极和漏极各自连接到电源和稳压器输出。 电压调节器输出连接到偏置在饱和模式的NMOS晶体管和一系列两个电阻。 运算放大器的非反相输入端连接在第一个反馈回路的两个电阻之间。 运算放大器的第二个输出通过用于第二反馈回路的交流耦合电容器连接到NMOS晶体管的栅极。 运算放大器的第一个输出可以通过电容连接到电源电压，以进一步提高高频PSRR。 在另一个实施例中，PMOS和NMOS晶体管的作用相反。

公开(公告)号：US20120044008A1

公开(公告)日：2012-02-23

申请号：US12859456

申请日：2010-08-19

申请人： Chan-Hong CHERN ,  Fu-Lung HSUEH ,  Chih-Chang LIN ,  Yuwen SWEI ,  Ming-Chieh HUANG

发明人： Chan-Hong CHERN ,  Fu-Lung HSUEH ,  Chih-Chang LIN ,  Yuwen SWEI ,  Ming-Chieh HUANG

IPC分类号： H03L5/00

CPC分类号： H03K3/02 ,  H03K19/018521 ,  H03K19/018528

摘要： A level shifter includes an input node, an output node, a pull-up transistor, a pull-down transistor, and at least one diode-connected device coupled between the pull-up transistor and the pull-down transistor. The level shifter is arranged to be coupled to a high power supply voltage, to receive an input signal having a first voltage level at the input node, and to supply an output signal having a second voltage level at the output node. The high power supply voltage is higher than the first voltage level. The at least one diode-connected device allows the output signal to be pulled up to about a first diode voltage drop below the high power supply voltage and/or to be pulled down to about a second diode voltage drop above ground. The first diode voltage drop and the second diode voltage drop are from the at least one diode-connected device.

摘要翻译： 电平移位器包括输入节点，输出节点，上拉晶体管，下拉晶体管以及耦合在上拉晶体管和下拉晶体管之间的至少一个二极管连接器件。 电平移位器被布置为耦合到高电源电压，以在输入节点处接收具有第一电压电平的输入信号，并且在输出节点处提供具有第二电压电平的输出信号。 高电源电压高于第一电压电平。 所述至少一个二极管连接的装置允许输出信号被上拉到大约低于高电源电压的第一二极管电压降和/或被下拉到大约地面上的第二二极管电压降。 第一二极管电压降和第二二极管压降来自至少一个二极管连接的器件。

公开(公告)号：US20050225401A1

公开(公告)日：2005-10-13

申请号：US10815219

申请日：2004-03-30

申请人： Lewelyn D'Souza ,  Yuwen Swei

发明人： Lewelyn D'Souza ,  Yuwen Swei

IPC分类号： H03B1/00 ,  H03B5/24 ,  H03H11/16 ,  H03K3/011 ,  H03K3/03 ,  H03K5/00 ,  H03K5/13 ,  H03L7/08 ,  H03L7/099

CPC分类号： H03L7/0995 ,  H03K3/011 ,  H03K3/0322 ,  H03K5/133 ,  H03K2005/00026

摘要： A design for an inverting delay component of an oscillator is disclosed, which enables the oscillator to be more tolerant of parameter variations. This increased parameter variation tolerance allows the KVCO of the oscillator to vary less between the worst case scenario (where the components of the oscillator meet minimum specifications) and the best case scenario (where the components meet the maximum specifications). This in turn means that the worst case KVCO value will be significantly smaller than in the prior art. By using a significantly smaller KVCO value, the jitter experienced at the output of the oscillator will be substantially reduced. Thus, this design enables a low-jitter oscillator to be realized.

摘要翻译： 公开了一种用于振荡器的反相延迟分量的设计，其使得振荡器能够更容忍参数变化。 这种增加的参数变化公差允许振荡器的K VCO在最坏情况（其中振荡器的组件满足最小规范）和最佳情况（其中组件满足最大值）的情况下变化较小 规格）。 这又意味着最差情况下的VCO的值将比现有技术中的显着地小。 通过使用明显较小的VCO的值，在振荡器的输出处经历的抖动将显着减小。 因此，该设计使得能够实现低抖动振荡器。

公开(公告)号：US09134360B2

公开(公告)日：2015-09-15

申请号：US13547101

申请日：2012-07-12

申请人： Tao Wen Chung ,  Chan-Hong Chern ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Yuwen Swei

发明人： Tao Wen Chung ,  Chan-Hong Chern ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Yuwen Swei

IPC分类号： H03L5/00 ,  G01R31/26

CPC分类号： G01R31/2621

摘要： A circuit has a first circuit module including a first resistor and first and second transistors coupled in parallel with the first resistor. The first resistor and the first and second transistors are coupled together at a first node. An equivalent resistance across the first circuit module increases as a voltage of the first node is increased from a first voltage to a second voltage, and the equivalent resistance across the first circuit module decreases as the voltage of the first node is increased from the second voltage to a third voltage.

摘要翻译： 电路具有包括第一电阻器和与第一电阻器并联耦合的第一和第二晶体管的第一电路模块。 第一电阻器和第一和第二晶体管在第一节点耦合在一起。 当第一节点的电压从第一电压增加到第二电压时，跨第一电路模块的等效电阻增加，并且第一电路模块上的等效电阻随着第一节点的电压从第二电压增加而减小 到第三电压。

公开(公告)号：US08896352B2

公开(公告)日：2014-11-25

申请号：US13278742

申请日：2011-10-21

申请人： Ming-Chieh Huang ,  Tao Wen Chung ,  Chan-Hong Chern ,  Chih-Chang Lin ,  Yuwen Swei ,  Chiang Pu

发明人： Ming-Chieh Huang ,  Tao Wen Chung ,  Chan-Hong Chern ,  Chih-Chang Lin ,  Yuwen Swei ,  Chiang Pu

IPC分类号： H03K3/00

CPC分类号： H03H11/44 ,  H01S5/0427 ,  H04B10/504

摘要： A driver includes a first driver stage having at least one input node and at least one first output node. The first driver stage includes a T-coil structure that is disposed adjacent to the at least one first output node. The T-coil structure includes a first set of inductors each being operable to provide a first inductance. A second set of inductors are electrically coupled with the first set of inductors in a parallel fashion. The second set of inductors each are operable to provide a second inductance. A second driver stage is electrically coupled with the first driver stage.

摘要翻译： 驱动器包括具有至少一个输入节点和至少一个第一输出节点的第一驱动器级。 第一驱动级包括邻近于至少一个第一输出节点设置的T型线圈结构。 T型线圈结构包括第一组电感器，每个电感器可操作以提供第一电感。 第二组电感器以并行方式与第一组电感器电耦合。 第二组电感器可操作以提供第二电感。 第二驱动级与第一驱动器级电耦合。