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公开(公告)号：US11816037B2
公开(公告)日：2023-11-14
申请号：US16712129
申请日：2019-12-12
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Steven Raasch , Andrew G. Kegel
IPC: G06F12/10 , G06F12/1009 , G06F12/1027 , G06F12/123 , G06F9/50 , G06F12/0871 , G06F12/02 , G06F11/07 , G06F12/0882
CPC classification number: G06F12/1009 , G06F9/5016 , G06F11/0772 , G06F12/0246 , G06F12/0871 , G06F12/0882 , G06F12/1027 , G06F12/123
Abstract: A processing system includes a primary processor and a co-processor. The primary processor is couplable to a memory subsystem having at least one memory and operating to execute system software employing memory address translations based on one or more page tables stored in the memory subsystem. The co-processor is likewise couplable to the memory subsystem and operates to perform iterations of a page table walk through one or more page tables maintained for the memory subsystem and to perform one or more page management operations on behalf of the system software based the iterations of the page table walk. The page management operations performed by the co-processor include analytic data aggregation, free list management and page allocation, page migration management, page table error detection, and the like.
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公开(公告)号：US11294747B2
公开(公告)日：2022-04-05
申请号：US15884638
申请日：2018-01-31
Applicant: Advanced Micro Devices, Inc.
Inventor： Andrew G. Kegel , David A. Roberts
Abstract: A neural network runs a known input data set using an error free power setting and using an error prone power setting. The differences in the outputs of the neural network using the two different power settings determine a high level error rate associated with the output of the neural network using the error prone power setting. If the high level error rate is excessive, the error prone power setting is adjusted to reduce errors by changing voltage and/or clock frequency utilized by the neural network system. If the high level error rate is within bounds, the error prone power setting can remain allowing the neural network to operate with an acceptable error tolerance and improved efficiency. The error tolerance can be specified by the neural network application.
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公开(公告)号：US10970118B2
公开(公告)日：2021-04-06
申请号：US15974014
申请日：2018-05-08
Applicant: Advanced Micro Devices, Inc.
Inventor： Andrew G. Kegel , David A. Roberts
Abstract: Systems, apparatuses, and methods for sharing an field programmable gate array compute engine are disclosed. A system includes one or more processors and one or more FPGAs. The system receives a request, generated by a first user process, to allocate a portion of processing resources on a first FPGA. The system maps the portion of processing resources of the first FPGA into an address space of the first user process. The system prevents other user processes from accessing the portion of processing resources of the first FPGA. Later, the system detects a release of the portion of the processing resources on the first FPGA by the first user process. Then, the system receives a second request to allocate the first FPGA from a second user process. In response to the second request, the system maps the first FPGA into an address space of the second user process.
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公开(公告)号：US20200301849A1
公开(公告)日：2020-09-24
申请号：US16894473
申请日：2020-06-05
Applicant: Advanced Micro Devices, Inc.
Inventor： Sergey Blagodurov , Andrew G. Kegel
IPC: G06F12/1009 , G06F12/1081 , G06F12/1027 , G06F3/06
Abstract: The described embodiments include an input-output memory management unit (IOMMU) with two or more memory elements and a controller. The controller is configured to select, based on one or more factors, one or more selected memory elements from among the two or more memory elements for performing virtual address to physical address translations in the IOMMU. The controller then performs the virtual address to physical address translations using the one or more selected memory elements.
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公开(公告)号：US10585826B2
公开(公告)日：2020-03-10
申请号：US15005378
申请日：2016-01-25
Applicant: Advanced Micro Devices, Inc.
Inventor： Nuwan S. Jayasena , Andrew G. Kegel
IPC: G06F13/24
Abstract: The described embodiments include a computing device with multiple interrupt processors for processing interrupts. In the described embodiments, each of the multiple processors is classified as one or more processor types based on factors such as features and functionality of the processor, an operating environment of the processor, the characteristics of some or all of the available interrupts, etc. During operation, an interrupt controller in the computing device receives an indication of an interrupt. The interrupt controller then determines a processor type for processing the interrupt. Next, the interrupt controller causes the interrupt to be processed by one of the plurality of processors that is the determined processor type.
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公开(公告)号：US09304955B2
公开(公告)日：2016-04-05
申请号：US13718841
申请日：2012-12-18
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Andrew G. Kegel
CPC classification number: G06F13/24 , G06F21/572 , G06F21/74 , G06F21/82
Abstract: A method for identifying and reporting interrupt behavior includes incrementing a counter when an interrupt signal is a designated type and is not received from an approved peripheral device, and performing a corrective action when the counter reaches a threshold value. In some embodiments, the designated type of the interrupt signal comprises a System Management Interrupt (SMI), which has the capability of halting operations at all processors within a system to execute associated instructions within a protected circumstance, resuming normal operations for each of the plurality of processors when the corrective action has been completed. In another embodiment, the corrective action includes creating a report identifying, within the same protected circumstance, the interrupt signal as an SMI. In some embodiments, the method performs a different corrective action when an interrupt signal is a designated type and is received from an approved peripheral device and decrements a counter. In some embodiments, the interrupt signal includes information indicating its source.
Abstract translation: 一种用于识别和报告中断行为的方法包括当中断信号是指定类型时增加计数器，并且不从批准的外围设备接收，并且当计数器达到阈值时执行校正动作。 在一些实施例中，指定类型的中断信号包括系统管理中断（SMI），该系统管理中断具有在系统内的所有处理器上停止操作的能力，以在受保护的环境内执行相关联的指令，恢复对于多个 的处理器，当纠正措施已经完成。 在另一个实施例中，纠正措施包括在相同的受保护的环境中创建一个报告，将中断信号标识为SMI。 在一些实施例中，当中断信号是指定类型并且从批准的外围设备接收并递减计数器时，该方法执行不同的校正动作。 在一些实施例中，中断信号包括指示其源的信息。
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7.发明授权Secure computer system for preventing access requests to portions of system memory by peripheral devices and/or processor cores 有权安全的计算机系统，用于防止外围设备和/或处理器核心对系统内存部分的访问请求
公开(公告)号：US09063891B2
公开(公告)日：2015-06-23
申请号：US13719671
申请日：2012-12-19
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Andrew G. Kegel
CPC classification number: G06F12/1441 , G06F12/1081 , G06F21/604 , G06F21/78
Abstract: A computer system is provided for preventing peripheral devices and/or processor cores from accessing restricted portions of system memory. For example, the computer system can include a host bridge, system memory coupled to the host bridge via a first access bus, a security processor coupled to the host bridge via a memory access bus that allows the security processor to access system memory and to access the peripheral device, and a security processor memory management unit (SPMMU) coupled between the peripheral device and the host bridge. The security processor is configured to program the SPMMU via the memory access bus to specify a first restricted range of physical addresses in the system memory that the peripheral device is not permitted to access. The SPMMU can then process access requests from the peripheral device and deny access requests that are determined to be within the first restricted range.
Abstract translation: 提供了一种用于防止外围设备和/或处理器核心访问系统存储器的限制部分的计算机系统。 例如，计算机系统可以包括主桥，经由第一访问总线耦合到主桥的系统存储器，经由存储器访问总线耦合到主桥的安全处理器，其允许安全处理器访问系统存储器并访问 外围设备和耦合在外围设备和主机桥之间的安全处理器存储器管理单元（SPMMU）。 安全处理器被配置为经由存储器访问总线对SPMMU进行编程，以指定外部设备不被允许访问的系统存储器中的物理地址的第一受限范围。 SPMMU然后可以处理来自外围设备的访问请求，并拒绝被确定在第一限制范围内的访问请求。
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公开(公告)号：US20140181361A1
公开(公告)日：2014-06-26
申请号：US13725177
申请日：2012-12-21
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Andrew G. Kegel
IPC: G06F12/06
CPC classification number: G06F12/0638 , G06F3/0679 , G06F11/0751 , G06F11/2015 , G06F12/0804 , G06F12/0866
Abstract: Memory units and computer systems are provided. The computer systems include a memory unit. The memory unit includes a stable storage unit, an unstable storage unit, and a controller. The unstable storage unit stores pending write operations for the stable storage unit. The controller is configured to determine the locations in the unstable storage that store the pending write information and to selectively write the pending write operations to the stable storage unit when power to the memory unit is interrupted.
Abstract translation: 提供内存单元和计算机系统。 计算机系统包括存储单元。 存储单元包括稳定存储单元，不稳定存储单元和控制器。 不稳定存储单元存储稳定存储单元的待处理写入操作。 控制器被配置为确定存储未决写入信息的不稳定存储器中的位置，并且当对存储器单元的电力中断时，有选择地将待决写入操作写入稳定存储单元。
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公开(公告)号：US12182412B2
公开(公告)日：2024-12-31
申请号：US17368461
申请日：2021-07-06
Applicant: Advanced Micro Devices, Inc.
Inventor： Andrew G. Kegel , Steven E. Raasch
IPC: G06F3/06 , G06F12/0891 , G06F16/907
Abstract: An electronic device includes a non-volatile memory and a memory controller. The memory controller selects, from the type-duration table, a duration for which data of a type of data is to be stored in a non-volatile memory. The memory controller writes the data to the non-volatile memory using values of one or more write parameters selected by the memory controller based on the duration. The memory controller sets an expected lifetime value in a record for the data in the expected lifetime table to indicate an expected lifetime of the data in the non-volatile memory.
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公开(公告)号：US12008371B2
公开(公告)日：2024-06-11
申请号：US17886855
申请日：2022-08-12
Applicant: Advanced Micro Devices, Inc.
Inventor： Andrew G. Kegel
CPC classification number: G06F9/30123 , G06F9/30043 , G06F9/30079 , G06F9/4881 , G06F30/34
Abstract: Systems, apparatuses, and methods for implementing as part of a processor pipeline a reprogrammable execution unit capable of executing specialized instructions are disclosed. A processor includes one or more reprogrammable execution units which can be programmed to execute different types of customized instructions. When the processor loads a program for execution, the processor loads a bitfile associated with the program. The processor programs a reprogrammable execution unit with the bitfile so that the reprogrammable execution unit is capable of executing specialized instructions associated with the program. During execution, a dispatch unit dispatches the specialized instructions to the reprogrammable execution unit for execution. The results of other instructions, such as integer and floating point instructions, are available immediately to instructions executing on the reprogrammable execution unit since the reprogrammable execution unit shares the processor registers with the integer and floating point execution units.
