-
公开(公告)号:US12107076B2
公开(公告)日:2024-10-01
申请号:US17564137
申请日:2021-12-28
Applicant: ADVANCED MICRO DEVICES, INC. , ATI TECHNOLOGIES ULC
Inventor: Wonjun Jung , Jasmeet Singh Narang , Tyrone Huang , Christopher Klement , Alan D. Smith , Edward Chang , John Wuu
IPC: H01L25/065 , H01L23/48
CPC classification number: H01L25/0657 , H01L23/481 , H01L25/0652 , H01L2225/06544
Abstract: Integrated circuits and integrated circuit dies include TSVs laid out in symmetrical patterns. Because of the symmetrical arrangement of the TSVs and associated routing patterns, an integrated circuit is able to support operation of multiple similar dies that are placed in different positions in the integrated circuit. This in turn simplifies the design and production of the multiple similar dies, thus reducing development and manufacturing costs for the corresponding integrated circuits.
-
公开(公告)号:US20240324248A1
公开(公告)日:2024-09-26
申请号:US18474179
申请日:2023-09-25
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor: John Wuu , Kevin Gillespie , Samuel Naffziger , Spence Oliver , Rajit Seahra , Regina T. Schmidt , Raja Swaminathan , Omar Zia
IPC: H10B80/00 , H01L23/544 , H01L25/00 , H01L25/18
CPC classification number: H10B80/00 , H01L23/544 , H01L25/18 , H01L25/50 , H01L23/481 , H01L23/5286 , H01L24/06 , H01L24/08 , H01L2223/54433 , H01L2224/06181 , H01L2224/08145
Abstract: A method for die pair partitioning can include providing a circuit die. The method can additionally include providing one or more additional circuit die having one or more fuses positioned therein, wherein the one or more fuses identify the circuit die. The method can also include connecting the one or more additional circuit die to the circuit die. Various other methods, systems, and computer-readable media are also disclosed.
-
公开(公告)号:US10303398B2
公开(公告)日:2019-05-28
申请号:US15794457
申请日:2017-10-26
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor: John Wuu , Michael K. Ciraula , Russell Schreiber , Samuel Naffziger
IPC: G11C5/06 , G06F3/06 , G06F12/1009
Abstract: A processing system includes a compute die and a stacked memory stacked with the compute die. The stacked memory includes a first memory die and a second memory die stacked on top of the first memory die. A parallel access using a single memory address is directed towards different memory banks of the first memory die and the second memory die. The single memory address of the parallel access is swizzled to access the first memory die and the second memory die at different physical locations.
-
公开(公告)号:US20240321706A1
公开(公告)日:2024-09-26
申请号:US18474151
申请日:2023-09-25
Applicant: Advanced Micro Devices, Inc.
Inventor: William George En , Samuel Naffziger , Regina T. Schmidt , Omar Zia , John Wuu
IPC: H01L23/498 , H01L23/48 , H01L25/065
CPC classification number: H01L23/49827 , H01L23/481 , H01L23/49816 , H01L25/0657 , H01L2225/06541
Abstract: A method for implementing shared metal connectivity between 3D stacked circuit dies can include providing a first circuit die having a first metal stack. The method can additionally include providing a second circuit die having a second metal stack, wherein at least one metal layer of the second metal stack is utilized by both the first circuit die and the second circuit die. The method can also include connecting the second metal stack to the first metal stack of the first circuit die. Various other methods, systems, and computer-readable media are also disclosed.
-
公开(公告)号:US11164807B2
公开(公告)日:2021-11-02
申请号:US16563077
申请日:2019-09-06
Applicant: Advanced Micro Devices, Inc.
Inventor: John Wuu , Samuel Naffziger , Patrick J. Shyvers , Milind S. Bhagavat , Kaushik Mysore , Brett P. Wilkerson
IPC: H01L23/367 , H01L25/00 , H01L25/065 , H01L23/36 , H01L23/373
Abstract: Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a floor plan with a high heat producing area and a low heat producing area. At least one second semiconductor chip is stacked on the low heat producing area. The semiconductor chip device also includes means for transferring heat from the high heat producing area.
-
公开(公告)号:US20150318056A1
公开(公告)日:2015-11-05
申请号:US14266039
申请日:2014-04-30
Applicant: Advanced Micro Devices Inc.
Inventor: Amlan Ghosh , Keith Allen Kasprak , John Wuu , John Reginald Riley, III
IPC: G11C29/02 , G11C11/419
CPC classification number: G11C29/02 , G11C11/41 , G11C11/419 , G11C29/50012 , G11C29/56 , G11C2029/5006
Abstract: A test circuit for a static random access memory (SRAM) array includes a plurality of stages coupled in a ring. Each stage includes a plurality of bit cells to store information, a bit line and a complementary bit line coupled to the plurality of bit cells, and a plurality of word lines coupled to the plurality of bit cells. Subsets of the plurality of word lines of each of the plurality of stages are selectively enabled based on signals asserted on the complementary bit line of another one of the plurality of stages. The test circuit also includes inversion logic deployed between two of the plurality of stages.
Abstract translation: 用于静态随机存取存储器(SRAM)阵列的测试电路包括以环形耦合的多个级。 每个级包括多个比特单元,用于存储耦合到多个比特单元的信息,位线和互补位线以及耦合到多个比特单元的多个字线。 基于在多个级中的另一个级的互补位线上断言的信号来选择性地使能多级级中的每一级的多个字线的子集。 测试电路还包括部署在多个级中的两个级之间的反相逻辑。
-
公开(公告)号:US11822484B2
公开(公告)日:2023-11-21
申请号:US17556257
申请日:2021-12-20
Applicant: Advanced Micro Devices, Inc.
Inventor: Vydhyanathan Kalyanasundharam , John Wuu , Chintan S. Patel
IPC: G06F12/08 , G06F12/0895 , G06F13/16 , G06F12/0891 , G06F12/0811
CPC classification number: G06F12/0895 , G06F12/0811 , G06F12/0891 , G06F13/1668
Abstract: A cache includes an upstream port, a cache memory for storing cache lines each having a line width, and a cache controller. The cache controller is coupled to the upstream port and the cache memory. The upstream port transfers data words having a transfer width less than the line width. In response to a cache line fill, the cache controller selectively determines data bus inversion information for a sequence of data words having the transfer width, and stores the data bus inversion information along with selected inverted data words for the cache line fill in the cache memory.
-
公开(公告)号:US11189540B2
公开(公告)日:2021-11-30
申请号:US16563138
申请日:2019-09-06
Applicant: Advanced Micro Devices, Inc.
Inventor: John Wuu , Samuel Naffziger , Patrick J. Shyvers , Milind S. Bhagavat , Kaushik Mysore , Brett P. Wilkerson
IPC: H01L23/367 , H01L25/00 , H01L25/065 , H01L23/36 , H01L23/373
Abstract: Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a floor plan with a high heat producing area and a low heat producing area. At least one second semiconductor chip is stacked on the low heat producing area. The semiconductor chip device also includes means for transferring heat from the high heat producing area.
-
公开(公告)号:US20240321702A1
公开(公告)日:2024-09-26
申请号:US18474166
申请日:2023-09-25
Applicant: Advanced Micro Devices, Inc. , Xilinx, Inc.
Inventor: Yan Wang , Kevin Gillespie , Samuel Naffziger , Richard Schultz , Raja Swaminathan , Omar Zia , John Wuu
IPC: H01L23/498 , H01L23/00 , H01L23/367 , H01L25/065
CPC classification number: H01L23/49822 , H01L23/3675 , H01L23/49816 , H01L24/05 , H01L24/32 , H01L25/0652 , H01L2224/05009 , H01L2224/05025 , H01L2224/32146 , H01L2224/32165 , H01L2924/1431 , H01L2924/1437 , H01L2924/351
Abstract: A method for providing backside power can include providing a first circuit die having a first metal stack. The method can also include connecting a second metal stack of a second circuit die to the first metal stack of the first circuit die, wherein a backside power delivery network is located in a passivation layer of at least one of the first circuit die or the second circuit die. Various other methods, systems, and computer-readable media are also disclosed.
-
公开(公告)号:US20230195642A1
公开(公告)日:2023-06-22
申请号:US17556257
申请日:2021-12-20
Applicant: Advanced Micro Devices, Inc.
Inventor: Vydhyanathan Kalyanasundharam , John Wuu , Chintan S. Patel
IPC: G06F12/0895 , G06F12/0811 , G06F12/0891 , G06F13/16
CPC classification number: G06F12/0895 , G06F12/0811 , G06F12/0891 , G06F13/1668
Abstract: A cache includes an upstream port, a cache memory for storing cache lines each having a line width, and a cache controller. The cache controller is coupled to the upstream port and the cache memory. The upstream port transfers data words having a transfer width less than the line width. In response to a cache line fill, the cache controller selectively determines data bus inversion information for a sequence of data words having the transfer width, and stores the data bus inversion information along with selected inverted data words for the cache line fill in the cache memory.