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13 条记录 (耗时 0.014 秒)

    Self-balanced silicon-controlled rectification device
    1.
    发明授权
    Self-balanced silicon-controlled rectification device 有权

    公开(公告)号：US09748219B1

    公开(公告)日：2017-08-29

    申请号：US15241365

    申请日：2016-08-19

    申请人： AMAZING MICROELECTRONIC CORP.

    发明人： Ming-Dou Ker ,  Woei-Lin Wu ,  James Jeng-Jie Peng ,  Ryan Hsin-Chin Jiang

    IPC分类号： H01L27/02 ,  H01L23/528

    CPC分类号： H01L27/0262 ,  H01L23/528 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/87

    摘要： A self-balanced silicon-controlled rectification device includes a substrate, an N-type doped well, a P-type doped well, at least one heavily doped clamping fin, at least one first P-type heavily doped fin, and at least one first N-type heavily doped fin. The N-type doped well and the P-type doped well are arranged in the substrate. The heavily doped clamping fin is arranged in the N-type doped well and the P-type well and protruded up from a surface of the substrate. The first P-type heavily doped fin and the first N-type heavily doped fin are respectively arranged in the N-type doped well and the P-type doped well, and protruded up from the surface of the substrate. The abovementioned elements forms silicon-controlled rectifiers (SCRs) are forward biased to generate uniform electrostatic discharge (ESD) currents through the SCRs.

    Slope control circuit
    4.
    发明授权
    Slope control circuit 有权

    公开(公告)号：US09608606B2

    公开(公告)日：2017-03-28

    申请号：US14955613

    申请日：2015-12-01

    申请人： AMAZING MICROELECTRONIC CORP.

    发明人： Long-Xi Chang ,  Ryan Hsin-Chin Jiang

    IPC分类号： H03K5/01 ,  H03K3/353

    CPC分类号： H03K5/01 ,  H03K3/353 ,  H03K19/00361

    摘要： A slope control circuit is connected between a replica circuit and a controller area network bus. The replica circuit generates an upper and a lower feedback signal. The slope control circuit receives and is driven by the feedback signals for controlling a voltage slope of a high-level output and a low-level output. The slope control circuit comprises an upper and a lower driving circuit, individually connected between the replica circuit, the high-level output and the low-level output. The upper driving circuit and the lower driving circuit respectively include at least one charging and discharging circuit. By controlling the charging and discharging circuit, the present invention controls decreasing voltage slope of the high-level output to be symmetric to increasing voltage slope of the low-level output, and delay time of the circuit switching between different operating modes to be equivalent.

    Splicing type electret loudspeaker
    5.
    发明授权
    Splicing type electret loudspeaker 有权
    拼接型驻极体扬声器

    公开(公告)号：US09462394B2

    公开(公告)日：2016-10-04

    申请号：US14587827

    申请日：2014-12-31

    申请人： AMAZING MICROELECTRONIC CORP.

    发明人： Mou-Ong Sher ,  Ryan Hsin-Chin Jiang ,  Ming-Che Hsieh

    IPC分类号： H04R25/00 ,  H04R19/01

    CPC分类号： H04R19/013 ,  H04R1/021 ,  H04R1/028 ,  H04R2201/021 ,  H04R2420/07

    摘要： The present invention discloses a splicing type electret loudspeaker. The splicing type electret loudspeaker may comprise a plurality of electret loudspeaker units. Each electret loudspeaker unit may comprise a plurality of connection ports, and these connection ports may be disposed around the edge of each electret loudspeaker unit. In particular, the connection ports of each electret loudspeaker unit can respectively connect to one of the connection ports of another electret loudspeaker unit; in this way, these electret loudspeaker units can connect to each other in parallel, such that the power input signal and the audio input signal can be transmitted to all electret loudspeaker units to drive them.

    摘要翻译： 本发明公开了一种拼接型驻极体扬声器。 拼接型驻极体扬声器可以包括多个驻极体扬声器单元。 每个驻极体扬声器单元可以包括多个连接端口，并且这些连接端口可以设置在每个驻极体扬声器单元的边缘周围。 特别地，每个驻极体扬声器单元的连接端口可以分别连接到另一个驻极体扬声器单元的一个连接端口; 以这种方式，这些驻极体扬声器单元可以彼此并联连接，使得功率输入信号和音频输入信号可以传输到所有驻极体扬声器单元以驱动它们。

    Serial transmission driving method
    6.
    发明授权
    Serial transmission driving method 有权
    串行传输驱动方式

    公开(公告)号：US09264042B2

    公开(公告)日：2016-02-16

    申请号：US14199448

    申请日：2014-03-06

    申请人： Amazing Microelectronic Corp.

    发明人： Tang-Kuei Tseng ,  Chih-Hao Chen ,  Szu-Hsien Wu ,  Ryan Hsin-Chin Jiang

    IPC分类号： H03K19/0175 ,  H03K19/00 ,  H04B1/38 ,  H04L5/16 ,  H03K19/003 ,  H03K19/01

    CPC分类号： H03K19/00346 ,  H03K19/0005 ,  H03K19/01 ,  H03K19/017509

    摘要： The present invention discloses a serial transmission driving method, wherein a serial transmission driving device (STD) is connected with a first terminal (FT) and a second terminal (ST) of an equivalent load capacitor through a first differential bus (FDB) and a second differential bus (SDB). FDB and SDB are respectively connected with a high-potential terminal (HPT) and a low-potential terminal (LPT) through a first equivalent resistor and a second equivalent resistor. STD receives a trigger signal (TS) appearing during the transition between a turn-on signal (Ton) and a turn-off signal (Toff), generates a first potential (FP) and a second potential (SP) greater than FP according to TS, and respectively applies FP and SP to SDB and FDB. FP and SP fast change the potential of FT to be greater than that of ST. HPT and LPT maintain potentials of FDB and SDB until Toff ends.

    摘要翻译： 本发明公开了一种串行传输驱动方法，其中串行传输驱动装置（STD）通过第一差分总线（FDB）与等效负载电容器的第一端子（FT）和第二端子（ST）连接， 第二差分总线（SDB）。 FDB和SDB分别通过第一等效电阻器和第二等效电阻器与高电位端子（HPT）和低电位端子（LPT）连接。 STD接收在导通信号（Ton）和关断信号（Toff）之间的转换期间出现的触发信号（TS），根据下列情况产生大于FP的第一电位（FP）和第二电位（SP） TS，并分别将FP和SP应用于SDB和FDB。 FP和SP快速将FT的潜力更大于ST的潜力。 HPT和LPT保持FDB和SDB的潜力，直到Toff结束。

    Method for fabricating a planar micro-tube discharger structure
    7.
    发明授权
    Method for fabricating a planar micro-tube discharger structure 有权
    平面微管放电器结构的制造方法

    公开(公告)号：US09024516B2

    公开(公告)日：2015-05-05

    申请号：US14109297

    申请日：2013-12-17

    申请人： Amazing Microelectronic Corp.

    发明人： Tung-Yang Chen ,  Ming-Dou Ker ,  Ryan Hsin-Chin Jiang

    IPC分类号： H01J1/88 ,  H01J19/42 ,  H01K1/18 ,  H02H9/00 ,  H01H47/00 ,  H05F3/00 ,  H01J9/02 ,  H01J17/06

    CPC分类号： H01J9/02 ,  H01J17/066

    摘要： A method for fabricating a semiconductor-based planar micro-tube discharger structure is provided, including the steps of forming on a substrate two patterned electrodes separated by a gap and at least one separating block arranged in the gap, forming an insulating layer over the patterned electrodes and the separating block, and filling the insulating layer into the gap. At least two discharge paths are formed. The method can fabricate a plurality of discharge paths in a semiconductor structure, the structure having very high reliability and reusability.

    摘要翻译： 提供一种制造基于半导体的平面微管放电器结构的方法，包括以下步骤：在衬底上形成由间隙分开的两个图案化电极和布置在间隙中的至少一个分隔块，在图案上形成绝缘层 电极和分离块，并将绝缘层填充到间隙中。 形成至少两个排出路径。 该方法可以在半导体结构中制造多个放电路径，该结构具有非常高的可靠性和可再利用性。

    Silicon-controlled rectification device with high efficiency
    8.
    发明授权
    Silicon-controlled rectification device with high efficiency 有权
    硅控整流装置效率高

    公开(公告)号：US09024354B2

    公开(公告)日：2015-05-05

    申请号：US13959882

    申请日：2013-08-06

    申请人： Amazing Microelectronic Corp.

    发明人： Tung-Yang Chen ,  James Jeng-Jie Peng ,  Woei-Lin Wu ,  Ryan Hsin-Chin Jiang

    IPC分类号： H01L29/66 ,  H01L29/74 ,  H01L29/861

    CPC分类号： H01L29/747 ,  H01L27/0262 ,  H01L29/7436 ,  H01L29/861

    摘要： A silicon-controlled rectification device with high efficiency is disclosed, which comprises a P-type region surrounding an N-type region. A first P-type heavily doped area is arranged in the N-type region and connected with a high-voltage terminal. A plurality of second N-type heavily doped areas is arranged in the N-type region. A plurality of second P-type heavily doped areas is closer to the second N-type heavily doped areas than the first N-type heavily doped area and arranged in the P-type region. At least one third N-type heavily doped area is arranged in the P-type region and connected with a low-voltage terminal. Alternatively or in combination, the second N-type heavily doped areas and the second P-type heavily doped areas are respectively arranged in the P-type region and the N-type region.

    摘要翻译： 公开了一种高效率的硅控整流装置，其包括围绕N型区域的P型区域。 第一P型重掺杂区域布置在N型区域中并与高压端子连接。 在N型区域中布置有多个第二N型重掺杂区域。 多个第二P型重掺杂区域比第一N型重掺杂区域更靠近第二N型重掺杂区域并且布置在P型区域中。 在P型区域中设置至少一个第三N型重掺杂区域，并与低电压端子连接。 或者或组合地，第二N型重掺杂区域和第二P型重掺杂区域分别布置在P型区域和N型区域中。

    Self-feedback control circuit
    9.
    发明授权
    Self-feedback control circuit 有权

    公开(公告)号：US09685936B2

    公开(公告)日：2017-06-20

    申请号：US14955571

    申请日：2015-12-01

    申请人： AMAZING MICROELECTRONIC CORP.

    发明人： Long-Xi Chang ,  Ryan Hsin-Chin Jiang

    IPC分类号： H03L5/00 ,  H03K5/003 ,  G06F13/40 ,  H03K19/0185

    CPC分类号： H03K5/003 ,  G06F13/4072 ,  H03K19/018521

    摘要： A self-feedback control circuit is connected to a controller area network bus for controlling a high-level output and a low-level output, comprising a controller area network driving circuit and a replica circuit. The replica circuit is connected in parallel with the controller area network driving circuit and comprises an upper feedback path and a lower feedback path. The upper feedback path and the lower feedback path are connected jointly to a common mode, and the replica circuit provides a feedback signal from the common mode such that the feedback signal is able to be respectively transmitted to two individual transistors of the controller area network driving circuit through the upper feedback path and through the lower feedback path so as to control DC level stability of the high-level output and the low-level output.