公开(公告)号：US20170098575A1

公开(公告)日：2017-04-06

申请号：US15285011

申请日：2016-10-04

Applicant: APPLIED MATERIALS, INC.

Inventor： Sree Rangasai V. KESAPRAGADA ,  Kevin MORAES ,  Srinivas GUGGILLA ,  He REN ,  Mehul NAIK ,  David THOMPSON ,  Weifeng YE ,  Yana CHENG ,  Yong CAO ,  Xianmin TANG ,  Paul F. MA ,  Deenesh PADHI

IPC: H01L21/768 ,  H01L21/02

CPC classification number: H01L21/76832 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/02178 ,  H01L21/02211 ,  H01L21/02219 ,  H01L21/02266 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/3105 ,  H01L21/32 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76834

Abstract: In some embodiments, a method of forming an interconnect structure includes selectively depositing a barrier layer atop a substrate having one or more exposed metal surfaces and one or more exposed dielectric surfaces, wherein a thickness of the barrier layer atop the one or more exposed metal surfaces is greater than the thickness of the barrier layer atop the one or more exposed dielectric surfaces. In some embodiments, a method of forming an interconnect structure includes depositing an etch stop layer comprising aluminum atop a substrate via a physical vapor deposition process; and depositing a barrier layer atop the etch stop layer via a chemical vapor deposition process, wherein the substrate is transferred from a physical vapor deposition chamber after depositing the etch stop layer to a chemical vapor deposition chamber without exposing the substrate to atmosphere.

公开(公告)号：US20160118260A1

公开(公告)日：2016-04-28

申请号：US14525555

申请日：2014-10-28

Applicant: Applied Materials, Inc.

Inventor： Bencherki MEBARKI ,  Annamalai LAKSHMANAN ,  Kaushal K. SINGH ,  Andrew COCKBURN ,  Ludovic GODET ,  Paul F. MA ,  Mehul NAIK

IPC: H01L21/285 ,  H01L21/768 ,  H01J37/32 ,  H01L21/268

CPC classification number: H01J37/32192 ,  C23C16/42 ,  C23C16/56 ,  H01J37/32091 ,  H01J37/32321 ,  H01J37/32339 ,  H01L21/2686 ,  H01L21/28556 ,  H01L21/32053 ,  H01L21/76885

Abstract: Methods and apparatus for forming a metal silicide as nanowires for back-end interconnection structures for semiconductor applications are provided. In one embodiment, the method includes forming a metal silicide layer on a substrate by a chemical vapor deposition process or a physical vapor deposition process, thermal treating the metal silicide layer in a processing chamber, applying a microwave power in the processing chamber while thermal treating the metal silicide layer; and maintaining a substrate temperature less than 400 degrees Celsius while thermal treating the metal silicide layer. In another embodiment, a method includes supplying a deposition gas mixture including at least a metal containing precursor and a reacting gas on a surface of a substrate, forming a plasma in the presence of the deposition gas mixture by exposure to microwave power, exposing the plasma to light radiation, and forming a metal silicide layer on the substrate from the deposition gas.

Abstract translation: 提供了用于形成用于半导体应用的后端互连结构的纳米线的金属硅化物的方法和装置。 在一个实施例中，该方法包括通过化学气相沉积工艺或物理气相沉积工艺在衬底上形成金属硅化物层，对处理室中的金属硅化物层进行热处理，在处理室中施加微波功率，同时热处理 金属硅化物层; 并且在热处理金属硅化物层的同时保持低于400摄氏度的衬底温度。 在另一个实施方案中，一种方法包括在衬底的表面上提供包含至少含金属的前体和反应气体的沉积气体混合物，通过暴露于微波功率在沉积气体混合物的存在下形成等离子体，使等离子体 以照射辐射，并从沉积气体在衬底上形成金属硅化物层。

公开(公告)号：US20170306488A1

公开(公告)日：2017-10-26

申请号：US15465526

申请日：2017-03-21

Applicant: APPLIED MATERIALS, INC.

Inventor： Daping YAO ,  Hyman W.H. LAM ,  Jiang LU ,  Dien-Yeh WU ,  Can XU ,  Paul F. MA ,  Mei CHANG

IPC: C23C16/458 ,  C23C16/455

CPC classification number: C23C16/458 ,  C23C16/4404 ,  C23C16/455 ,  C23C16/45512

Abstract: A gas feedthrough assembly and processing apparatus using the same are disclosed herein. In some embodiments, the gas feedthrough assembly, includes a dielectric body; at least one channel extending through the dielectric body; and a dielectric tube disposed within the at least one channel, wherein an inner diameter of the at least one channel is greater than an outer diameter of the dielectric tube such that a gap is formed between an outer wall of the dielectric tube and an inner wall of the at least one channel.

公开(公告)号：US20160204029A1

公开(公告)日：2016-07-14

申请号：US14975028

申请日：2015-12-18

Applicant: Applied Materials, Inc.

Inventor： Bencherki MEBARKI ,  Annamalai LAKSHMANAN ,  Kaushal K. SINGH ,  Paul F. MA ,  Mehul B. NAIK ,  Andrew COCKBURN ,  Ludovic GODET

IPC: H01L21/768 ,  H01L21/285

Abstract: Methods and apparatus for forming a metal silicide as nanowires for back-end interconnection structures for semiconductor applications are provided. In one embodiment, the method includes forming a metal silicide stack comprising as plurality of metal silicide layers on a substrate by a chemical vapor deposition process or a physical vapor deposition process, thermal treating the metal silicide stack in a processing chamber, applying a microwave power in the processing chamber while thermal treating the metal silicide layer; and maintaining a substrate temperature less than 400 degrees Celsius while thermal treating the metal silicide layer.

Abstract translation: 提供了用于形成用于半导体应用的后端互连结构的纳米线的金属硅化物的方法和装置。 在一个实施例中，该方法包括通过化学气相沉积工艺或物理气相沉积工艺在衬底上形成包含多个金属硅化物层的金属硅化物堆叠，对处理室中的金属硅化物堆进行热处理，施加微波功率 在处理室中，同时热处理金属硅化物层; 并且在热处理金属硅化物层的同时保持低于400摄氏度的衬底温度。

公开(公告)号：US20190027403A1

公开(公告)日：2019-01-24

申请号：US16140342

申请日：2018-09-24

Applicant: APPLIED MATERIALS, INC.

Inventor： Sree Rangasai V. KESAPRAGADA ,  Kevin MORAES ,  Srinivas GUGGILLA ,  He REN ,  Mehul NAIK ,  David THOMPSON ,  Weifeng YE ,  Yana CHENG ,  Yong CAO ,  Xianmin TANG ,  Paul F. MA ,  Deenesh PADHI

IPC: H01L21/768 ,  H01L21/02

CPC classification number: H01L21/76832 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/02178 ,  H01L21/02211 ,  H01L21/02219 ,  H01L21/02266 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/3105 ,  H01L21/32 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76834

Abstract: In some embodiments, a method of forming an interconnect structure includes selectively depositing a barrier layer atop a substrate having one or more exposed metal surfaces and one or more exposed dielectric surfaces, wherein a thickness of the barrier layer atop the one or more exposed metal surfaces is greater than the thickness of the barrier layer atop the one or more exposed dielectric surfaces. In some embodiments, a method of forming an interconnect structure includes depositing an etch stop layer comprising aluminum atop a substrate via a physical vapor deposition process; and depositing a barrier layer atop the etch stop layer via a chemical vapor deposition process, wherein the substrate is transferred from a physical vapor deposition chamber after depositing the etch stop layer to a chemical vapor deposition chamber without exposing the substrate to atmosphere.

公开(公告)号：US20160268207A1

公开(公告)日：2016-09-15

申请号：US14711135

申请日：2015-05-13

Applicant: Applied Materials, Inc.

Inventor： Mehul B. NAIK ,  Paul F. MA ,  Tae Hong HA ,  Srinivas GUGGILLA

IPC: H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/28556 ,  H01L21/76846

Abstract: A method and apparatus for forming an interconnect on a substrate is provided. A protective layer is formed on the substrate and in a via formed on the substrate wherein the protective layer is resistant to a halogen containing material. A barrier layer is formed on top of the protective layer. The barrier layer comprises a halogen containing material. A metal layer is deposited over the barrier layer. In another embodiment, the protective layer is selectively deposited in the via.

Abstract translation: 提供了一种用于在基板上形成互连的方法和装置。 在衬底上形成保护层，形成在衬底上的通孔中，其中保护层对含卤素材料具有耐受性。 在保护层的顶部形成阻挡层。 阻挡层包括含卤素材料。 在阻挡层上沉积金属层。 在另一个实施例中，保护层选择性地沉积在通孔中。

公开(公告)号：US20150255333A1

公开(公告)日：2015-09-10

申请号：US14717375

申请日：2015-05-20

Applicant: APPLIED MATERIALS, INC.

Inventor： Jiang LU ,  Hyoung-Chan HA ,  Paul F. MA ,  Seshadri GANGULI ,  Joseph F. AUBUCHON ,  Sang-ho YU ,  Murali K. NARASIMHAN

IPC: H01L21/768 ,  H01L21/285

CPC classification number: H01L21/76871 ,  C23C16/16 ,  C23C16/18 ,  C23C16/42 ,  C23C16/56 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/28568 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76864 ,  H01L21/76873

Abstract: Embodiments of the invention provide processes for depositing a cobalt layer on a barrier layer and subsequently depositing a conductive material, such as copper or a copper alloy, thereon. In one embodiment, a method for depositing materials on a substrate surface is provided which includes forming a barrier layer on a substrate, exposing the substrate to dicobalt hexacarbonyl butylacetylene (CCTBA) and hydrogen to form a cobalt layer on the barrier layer during a vapor deposition process (e.g., CVD or ALD), and depositing a conductive material over the cobalt layer. In some examples, the barrier layer and/or the cobalt layer may be exposed to a gas or a reagent during a treatment process, such as a thermal process, an in situ plasma process, or a remote plasma process.

公开(公告)号：US20190172686A1

公开(公告)日：2019-06-06

申请号：US16250763

申请日：2019-01-17

Applicant: Applied Materials, Inc.

Inventor： Bencherki MEBARKI ,  Annamalai LAKSHMANAN ,  Kaushal K. SINGH ,  Andrew COCKBURN ,  Ludovic GODET ,  Paul F. MA ,  Mehul B. NAIK

IPC: H01J37/32 ,  H01L21/768 ,  C23C16/42 ,  H01L21/3205 ,  C23C16/56 ,  H01L21/285 ,  H01L21/268

Abstract: Methods and apparatus for forming a metal silicide as nanowires for back-end interconnection structures for semiconductor applications are provided. In one embodiment, the method includes forming a metal silicide layer on a substrate by a chemical vapor deposition process or a physical vapor deposition process, thermal treating the metal silicide layer in a processing chamber, applying a microwave power in the processing chamber while thermal treating the metal silicide layer; and maintaining a substrate temperature less than 400 degrees Celsius while thermal treating the metal silicide layer. In another embodiment, a method includes supplying a deposition gas mixture including at least a metal containing precursor and a reacting gas on a surface of a substrate, forming a plasma in the presence of the deposition gas mixture by exposure to microwave power, exposing the plasma to light radiation, and forming a metal silicide layer on the substrate from the deposition gas.

公开(公告)号：US20170179252A1

公开(公告)日：2017-06-22

申请号：US15043883

申请日：2016-02-15

Applicant: APPLIED MATERIALS, INC.

Inventor： Wei V. TANG ,  Paul F. MA ,  Steven C. H. HUNG ,  Michael CHUDZIK ,  Siddarth KRISHNAN ,  Wenyu ZHANG ,  Seshadri GANGULI ,  Naomi YOSHIDA ,  Lin DONG ,  Yixiong YANG ,  Liqi WU ,  Shih Chung CHEN

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/51 ,  H01L29/786 ,  H01L21/02

CPC classification number: H01L29/66446 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78603 ,  H01L29/78681

Abstract: Semiconductor devices incorporating multi-threshold voltage structures and methods of forming such semiconductor devices are provided herein. In some embodiments of the present disclosure, a semiconductor device having a multi-threshold voltage structure includes: a substrate; a gate dielectric layer atop the substrate, wherein the gate dielectric layer comprises an interface layer and a high-k dielectric layer atop the interface layer; a lanthanum nitride layer deposited atop the high-k dielectric layer; an interface of the interface layer and the high-k dielectric layer comprising lanthanum species from the lanthanum nitride layer; and a gate electrode layer atop the lanthanum nitride layer.

公开(公告)号：US20160204027A1

公开(公告)日：2016-07-14

申请号：US14975231

申请日：2015-12-18

Applicant: Applied Materials, Inc.

Inventor： Annamalai LAKSHMANAN ,  Bencherki MEBARKI ,  Kaushal K. SINGH ,  Paul F. MA ,  Mehul B. NAIK ,  Andrew COCKBURN ,  Ludovic GODET

IPC: H01L21/768 ,  H01L21/285

CPC classification number: H01L21/76879 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/32053 ,  H01L21/76802 ,  H01L21/76876 ,  H01L21/76886 ,  H01L21/76889 ,  H01L23/53257 ,  H01L23/53271 ,  H01L2221/1094

Abstract: Methods for direct deposition of a metal silicide nanowire for back-end interconnection structures for semiconductor applications are provided. In one embodiment, the method includes positioning a substrate in a processing region of a process chamber, the substrate having a first surface comprising a non-dielectric material; and a dielectric layer formed on the first surface. An opening is formed in the dielectric layer, the opening exposing at least a portion of the first surface, the opening having sidewalls. A metal silicide seed is deposited in the opening using a PVD process, wherein the PVD process is performed with either no bias or a bias which creates deposition on the sidewall which is less than 1% of the deposition on the first surface. A metal silicide layer is then selectively deposited on the metal silicide seed using a metal-silicon organic precursor, creating the metal silicide nanowire.

Abstract translation: 提供了用于半导体应用的后端互连结构的金属硅化物纳米线的直接沉积的方法。 在一个实施例中，该方法包括将衬底定位在处理室的处理区域中，该衬底具有包含非电介质材料的第一表面; 以及形成在第一表面上的电介质层。 在电介质层中形成开口，该开口露出第一表面的至少一部分，该开口具有侧壁。 使用PVD工艺在开口中沉积金属硅化物种子，其中PVD工艺是在没有偏压或偏压的情况下进行的，其产生在侧壁上的沉积，其小于第一表面上的沉积的1％。 然后使用金属硅有机前体将金属硅化物层选择性地沉积在金属硅化物种子上，产生金属硅化物纳米线。