公开(公告)号：US09966955B2

公开(公告)日：2018-05-08

申请号：US15331536

申请日：2016-10-21

申请人： ARM Limited

发明人： Ranabir Dey ,  Vijaya Kumar Vinukonda ,  Mikael Rien ,  Vikas Murli Kyatsandra

IPC分类号： H03K19/0175 ,  H03K19/003 ,  H03K19/0948 ,  H03K19/0185

CPC分类号： H03K19/017509 ,  H03K19/00315 ,  H03K19/018521 ,  H03K19/0948

摘要： Various implementations described herein are directed to an integrated circuit. The integrated circuit may include signal generation circuitry that receives an input signal from a first voltage domain and generates multiple internal signals based on the input signal. The integrated circuit may include signal evaluation circuitry that receives the multiple internal signals from the signal generation circuitry and provides an intermediate signal based on the multiple internal signals. The integrated circuit may include signal conversion circuitry that receives the intermediate signal and provides an output signal for a second voltage domain based on the intermediate signal. The integrated circuit may include signal protection circuitry that receives the input signal from the first voltage domain, receives the intermediate signal from the signal evaluation circuitry, and allows the input signal until the intermediate signal transitions between a first state and a second state that is different than the first state.

公开(公告)号：US20200220529A1

公开(公告)日：2020-07-09

申请号：US16239498

申请日：2019-01-03

申请人： Arm Limited

发明人： Seshagiri Rao Bogi ,  Vinay Chenani ,  Biswanath Nayak ,  Vijaya Kumar Vinukonda

IPC分类号： H03K3/02 ,  H03K5/003 ,  H03K19/018 ,  H03K19/094

摘要： Various implementations described herein refer to an integrated circuit having a first stage and a second stage. The first stage has first transistors arranged as a diode, a first latch and feedback assist to facilitate shifting an input voltage in a first voltage domain to an output voltage in a second voltage domain. The first stage uses the diode and the first latch to reduce contention between the first latch and input transistors. The diode, the first latch and the feedback assist enable activation of the input transistors with the input voltage. The second stage has second transistors arranged as a second latch followed by output buffers that provide a buffered output voltage as feedback to the feedback assist of the first stage.

公开(公告)号：US20180083631A1

公开(公告)日：2018-03-22

申请号：US15823481

申请日：2017-11-27

申请人： ARM Limited

发明人： Ranabir Dey ,  Vijaya Kumar Vinukonda ,  Mikael Rien

IPC分类号： H03K19/0185

CPC分类号： H03K19/018521

摘要： The present invention provides a receiver circuit and method for receiving an input signal from a source voltage domain and converting the input signal into an output signal for a destination voltage domain. The source voltage domain operates from a supply voltage that exceeds a stressing threshold of components within the receiver circuitry, and the receiver circuitry is configured to operate from the supply voltage of the source voltage domain. The receiver circuitry comprises first internal signal generation circuitry configured to convert the input signal into a first internal signal in a first voltage range, and second internal signal generation circuitry configured to convert the input signal into a second internal signal in a second voltage range. Signal evaluation circuitry establishes a logic high voltage threshold and a logic low voltage threshold dependent on the supply voltage, and employs the first and second internal signals in order to detect based on the logic high voltage threshold and logic low voltage threshold when the input signal transitions between a logic low level and a logic high level (in either direction). Output generation circuitry then generates the output signal in dependence on the detection performed by the signal evaluation circuitry. The first voltage range and the second voltage range are such that the first internal signal and second internal signal will not exceed the stressing threshold of components in the signal evaluation circuitry. The receiver circuitry is able to reliably detect transitions in the input signal in situations where the supply voltage of the source voltage domain exceeds the stressing threshold of the receiver's components, but without overstress of the receiver's components.

公开(公告)号：US10784842B2

公开(公告)日：2020-09-22

申请号：US16239498

申请日：2019-01-03

申请人： Arm Limited

发明人： Seshagiri Rao Bogi ,  Vinay Chenani ,  Biswanath Nayak ,  Vijaya Kumar Vinukonda

IPC分类号： H03K3/02 ,  H03K19/094 ,  H03K19/018 ,  H03K5/003

摘要： Various implementations described herein refer to an integrated circuit having a first stage and a second stage. The first stage has first transistors arranged as a diode, a first latch and feedback assist to facilitate shifting an input voltage in a first voltage domain to an output voltage in a second voltage domain. The first stage uses the diode and the first latch to reduce contention between the first latch and input transistors. The diode, the first latch and the feedback assist enable activation of the input transistors with the input voltage. The second stage has second transistors arranged as a second latch followed by output buffers that provide a buffered output voltage as feedback to the feedback assist of the first stage.

公开(公告)号：US09806716B2

公开(公告)日：2017-10-31

申请号：US14814180

申请日：2015-07-30

申请人： ARM Limited

发明人： Ranabir Dey ,  Vijaya Kumar Vinukonda ,  Mikael Rien

IPC分类号： H03K19/003 ,  H03K19/00 ,  H03K19/0185 ,  H03K3/356

CPC分类号： H03K19/00315 ,  H03K3/35613 ,  H03K3/356165 ,  H03K3/356182 ,  H03K19/0013 ,  H03K19/00384 ,  H03K19/018521

摘要： Output signal generation circuitry 100 may be used for converting an input signal 110 from a source voltage domain to an output signal for a destination voltage domain, the destination voltage domain operating from a supply voltage that exceeds a stressing threshold of components within the output signal generation circuitry. The output signal generation circuitry may comprise level shifting circuitry 160 operating from the supply voltage, which is configured to generate at an output node 130 the output signal for the destination voltage domain in dependence on the input signal. The output signal generation circuitry may also comprise tracking circuitry 280A, 280B, 280C, 280D associated with at least one component of the level shifting circuitry to ensure that a voltage drop across the at least one component does not exceed the stressing threshold, wherein the tracking circuitry additionally introduces a delay in a change in the output signal in response to a change in the input signal. Timing compensation circuitry 180A, 180B may also be provided, to control the voltage on the output node in a manner to compensate for the delay introduced by the tracking circuitry.

公开(公告)号：US20160172350A1

公开(公告)日：2016-06-16

申请号：US14570142

申请日：2014-12-15

申请人： ARM Limited

发明人： Ranabir Dey ,  Abhinav Kumar ,  Vijaya Kumar Vinukonda ,  Fabrice Blanc

IPC分类号： H01L27/02 ,  H02H9/04 ,  H01L29/78

CPC分类号： H02H9/046 ,  H01L27/0285 ,  H01L29/78

摘要： Various implementations described herein are directed to an integrated circuit for electrostatic discharge (ESD) protection. The integrated circuit may include a detection stage having a resistor and a first capacitor cascaded with a second capacitor. The resistor and the first capacitor are arranged to define a triggering node configured to provide a triggering signal. The first capacitor and the second capacitor are arranged to define a reference node configured to provide a reference signal. The integrated circuit may include a first ESD clamping stage having a first transistor configured to provide a supply voltage to a first clamping transistor based on the triggering signal. The integrated circuit may include a second ESD clamping stage having a second transistor configured to receive the supply voltage from the first transistor and provide the supply voltage to a second clamping transistor based on the reference signal.

摘要翻译： 本文描述的各种实现涉及用于静电放电（ESD）保护的集成电路。 集成电路可以包括具有电阻器和与第二电容器级联的第一电容器的检测级。 电阻器和第一电容器被布置成限定被配置为提供触发信号的触发节点。 布置第一电容器和第二电容器以限定被配置为提供参考信号的参考节点。 集成电路可以包括第一ESD钳位级，其具有被配置为基于触发信号向第一钳位晶体管提供电源电压的第一晶体管。 集成电路可以包括第二ESD钳位级，其具有被配置为从第一晶体管接收电源电压并且基于参考信号将电源电压提供给第二钳位晶体管的第二晶体管。

公开(公告)号：US20160036441A1

公开(公告)日：2016-02-04

申请号：US14814180

申请日：2015-07-30

申请人： ARM Limited

发明人： Ranabir Dey ,  Vijaya Kumar Vinukonda ,  Mikael Rien

IPC分类号： H03K19/003 ,  H03K19/0185 ,  H03K19/00

CPC分类号： H03K19/00315 ,  H03K3/35613 ,  H03K3/356165 ,  H03K3/356182 ,  H03K19/0013 ,  H03K19/00384 ,  H03K19/018521

摘要： Output signal generation circuitry 100 may be used for converting an input signal 110 from a source voltage domain to an output signal for a destination voltage domain, the destination voltage domain operating from a supply voltage that exceeds a stressing threshold of components within the output signal generation circuitry. The output signal generation circuitry may comprise level shifting circuitry 160 operating from the supply voltage, which is configured to generate at an output node 130 the output signal for the destination voltage domain in dependence on the input signal. The output signal generation circuitry may also comprise tracking circuitry 280A, 280B, 280C, 280D associated with at least one component of the level shifting circuitry to ensure that a voltage drop across the at least one component does not exceed the stressing threshold, wherein the tracking circuitry additionally introduces a delay in a change in the output signal in response to a change in the input signal. Timing compensation circuitry 180A, 180B may also be provided, to control the voltage on the output node in a manner to compensate for the delay introduced by the tracking circuitry.

摘要翻译： 输出信号生成电路100可以用于将输入信号110从源极电压域转换为目的地电压域的输出信号，目的地电压域从超过输出信号生成中的分量的应力阈值的电源电压 电路。 输出信号产生电路可以包括从电源电压操作的电平移位电路160，电源电压被配置成根据输入信号在输出节点130处产生用于目的地电压域的输出信号。 输出信号产生电路还可以包括与电平移动电路的至少一个部件相关联的跟踪电路280A，280B，280C，280D，以确保穿过至少一个部件的电压降不超过应力阈值，其中跟踪 电路还响应于输入信号的变化而引入输出信号变化的延迟。 还可以提供定时补偿电路180A，180B以以补偿由跟踪电路引入的延迟的方式来控制输出节点上的电压。

公开(公告)号：US11422581B2

公开(公告)日：2022-08-23

申请号：US17000141

申请日：2020-08-21

申请人： Arm Limited

发明人： Ranabir Dey ,  Vijaya Kumar Vinukonda

IPC分类号： H03K3/023 ,  G05F3/20 ,  H03K3/0233 ,  H03K3/356 ,  G05F3/30

摘要： Various implementations described herein are related to a device having header circuitry with first transistors that are configured to receive a supply voltage and provide a dynamically biased voltage. The device may include reference generation circuitry having multiple amplifiers that are configured to receive the supply voltage and provide reference voltages based on the supply voltage. The device may include bias generation circuitry having second transistors configured to track changes in the dynamically biased voltage and adjust the dynamically biased voltage by generating bias voltages based on the reference voltages and by applying the bias voltages to the header circuitry so as to adjust the dynamically biased voltage.

公开(公告)号：US20220057824A1

公开(公告)日：2022-02-24

申请号：US17000141

申请日：2020-08-21

申请人： Arm Limited

发明人： Ranabir Dey ,  Vijaya Kumar Vinukonda

IPC分类号： G05F3/20 ,  G05F3/30 ,  H03K3/356 ,  H03K3/0233

摘要： Various implementations described herein are related to a device having header circuitry with first transistors that are configured to receive a supply voltage and provide a dynamically biased voltage. The device may include reference generation circuitry having multiple amplifiers that are configured to receive the supply voltage and provide reference voltages based on the supply voltage. The device may include bias generation circuitry having second transistors configured to track changes in the dynamically biased voltage and adjust the dynamically biased voltage by generating bias voltages based on the reference voltages and by applying the bias voltages to the header circuitry so as to adjust the dynamically biased voltage.

公开(公告)号：US11169590B2

公开(公告)日：2021-11-09

申请号：US16517216

申请日：2019-07-19

申请人： Arm Limited

发明人： Ranabir Dey ,  Vinay Chenani ,  Kundan Srivastava ,  Vijaya Kumar Vinukonda

IPC分类号： G06F1/00 ,  G06F1/3234 ,  G06F1/3225 ,  G06F1/3203

摘要： Various implementations described herein are directed to a device having an output pad that provides an input-output (IO) voltage from an IO power supply. The device may include core ramp detection circuitry that detects a first ramp of a core voltage from a core power supply and provides a core ramp sensing signal. The device may include output logic circuitry that couples the output pad to ground after receiving the core ramp sensing signal so as to reduce leakage of the IO power supply.