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    Enhanced capacitance deep trench capacitor for EDRAM
    5.
    发明授权
    Enhanced capacitance deep trench capacitor for EDRAM 有权
    EDRAM增强型电容深沟槽电容器

    公开(公告)号：US08354675B2

    公开(公告)日：2013-01-15

    申请号：US12775532

    申请日：2010-05-07

    申请人： Oh-jung Kwon ,  Junedong Lee ,  Chengwen Pei ,  Geng Wang

    发明人： Oh-jung Kwon ,  Junedong Lee ,  Chengwen Pei ,  Geng Wang

    IPC分类号： H01L27/108

    CPC分类号： H01L28/82 ,  H01L27/10867 ,  H01L29/66181

    摘要： A substrate including a stack of a handle substrate, an optional lower insulator layer, a doped polycrystalline semiconductor layer, an upper insulator layer, and a top semiconductor layer is provided. A deep trench is formed through the top semiconductor layer, the upper insulator layer, and the doped polycrystalline semiconductor layer. Exposed vertical surfaces of the polycrystalline semiconductor layer are crystallographically etched to form random facets in the deep trench, thereby increasing the total exposed surface area of the polycrystalline semiconductor layer in the deep trench. A node dielectric and at least one conductive material are deposited to fill the trench and to form a buried strap portion, which constitute a capacitor of an eDRAM. Access transistors and other logic devices can be formed.

    摘要翻译： 提供了包括手柄衬底，可选的下绝缘体层，掺杂多晶半导体层，上绝缘体层和顶部半导体层的衬底的衬底。 通过顶部半导体层，上部绝缘体层和掺杂多晶半导体层形成深沟槽。 多晶半导体层的暴露的垂直表面被晶体学蚀刻以在深沟槽中形成随机刻面，从而增加深沟槽中的多晶半导体层的总暴露表面积。 沉积节点电介质和至少一种导电材料以填充沟槽并形成构成eDRAM的电容器的掩埋带部分。 可以形成存取晶体管和其它逻辑器件。

    ENHANCED CAPACITANCE DEEP TRENCH CAPACITOR FOR EDRAM
    6.
    发明申请
    ENHANCED CAPACITANCE DEEP TRENCH CAPACITOR FOR EDRAM 有权
    EDRAM的增强电容深度电容器

    公开(公告)号：US20110272702A1

    公开(公告)日：2011-11-10

    申请号：US12775532

    申请日：2010-05-07

    申请人： Oh-jung Kwon ,  Junedong Lee ,  Chengwen Pei ,  Geng Wang

    发明人： Oh-jung Kwon ,  Junedong Lee ,  Chengwen Pei ,  Geng Wang

    IPC分类号： H01L27/108 ,  H01L21/8242

    CPC分类号： H01L28/82 ,  H01L27/10867 ,  H01L29/66181

    摘要： A substrate including a stack of a handle substrate, an optional lower insulator layer, a doped polycrystalline semiconductor layer, an upper insulator layer, and a top semiconductor layer is provided. A deep trench is formed through the top semiconductor layer, the upper insulator layer, and the doped polycrystalline semiconductor layer. Exposed vertical surfaces of the polycrystalline semiconductor layer are crystallographically etched to form random facets in the deep trench, thereby increasing the total exposed surface area of the polycrystalline semiconductor layer in the deep trench. A node dielectric and at least one conductive material are deposited to fill the trench and to form a buried strap portion, which constitute a capacitor of an eDRAM. Access transistors and other logic devices can be formed.

    摘要翻译： 提供了包括手柄衬底，可选的下绝缘体层，掺杂多晶半导体层，上绝缘体层和顶部半导体层的衬底的衬底。 通过顶部半导体层，上部绝缘体层和掺杂多晶半导体层形成深沟槽。 多晶半导体层的暴露的垂直表面被晶体学蚀刻以在深沟槽中形成随机刻面，从而增加深沟槽中的多晶半导体层的总暴露表面积。 沉积节点电介质和至少一种导电材料以填充沟槽并形成构成eDRAM的电容器的掩埋带部分。 可以形成存取晶体管和其它逻辑器件。

    Array and moat isolation structures and method of manufacture
    9.
    发明授权
    Array and moat isolation structures and method of manufacture 有权
    阵列和护城隔离结构及其制造方法

    公开(公告)号：US08673737B2

    公开(公告)日：2014-03-18

    申请号：US13274389

    申请日：2011-10-17

    申请人： Naoyoshi Kusaba ,  Oh-jung Kwon ,  Zhengwen Li ,  Hongwen Yan

    发明人： Naoyoshi Kusaba ,  Oh-jung Kwon ,  Zhengwen Li ,  Hongwen Yan

    IPC分类号： H01L21/76

    CPC分类号： H01L29/423 ,  H01L21/762 ,  H01L27/10805 ,  H01L27/10829 ,  H01L27/1087 ,  H01L29/66181 ,  H01L29/945

    摘要： An array or moat isolation structure for eDRAM and methods of manufacture is provided. The method includes forming a deep trench for a memory array and an isolation region. The method includes forming a node dielectric on exposed surfaces of the deep trench for the memory array and the isolation region. The method includes filling remaining portions of the deep trench for the memory array with a metal, and lining the deep trench of the isolation region with the metal. The method includes filling remaining portions of the deep trench for the isolation region with a material, on the metal within the deep trench for the memory array. The method includes recessing the metal within the deep trench for the memory array and the isolation region. The metal in the deep trench of the memory array is recessed to a greater depth than the metal in the isolation region.

    摘要翻译： 提供了一种用于eDRAM的阵列或护城隔离结构及其制造方法。 该方法包括形成用于存储器阵列的深沟槽和隔离区域。 该方法包括在用于存储器阵列和隔离区域的深沟槽的暴露表面上形成节点电介质。 该方法包括用金属填充用于存储器阵列的深沟槽的剩余部分，并用金属衬里隔离区域的深沟槽。 该方法包括用用于存储器阵列的深沟槽内的金属上的材料填充用于隔离区域的深沟槽的剩余部分。 该方法包括使用于存储器阵列和隔离区域的深沟槽内的金属凹陷。 存储器阵列的深沟槽中的金属凹陷到比隔离区域中的金属更深的深度。

    TEST PATTERN FOR MEASURING CONTACT SHORT AT FIRST METAL LEVEL
    10.
    发明申请
    TEST PATTERN FOR MEASURING CONTACT SHORT AT FIRST METAL LEVEL 审中-公开
    测量图形用于测量第一个金属水平的触点短路

    公开(公告)号：US20070210306A1

    公开(公告)日：2007-09-13

    申请号：US11308137

    申请日：2006-03-08

    申请人： Joyce Molinelli Acocella ,  Oh-jung Kwon

    发明人： Joyce Molinelli Acocella ,  Oh-jung Kwon

    IPC分类号： H01L23/58

    CPC分类号： H01L22/34

    摘要： The invention relates to a test structure and methods of detecting electrical defects between adjacent metal contacts using such test structure at the first metal level within a semiconductor device. The test structure includes dual first metal level comb structures each having extending lines that are in direct electrical communication with contacts residing in the semiconductor. The extending lines of the first metal comb are interlaced with extending lines on the second metal comb such that adjacent metal contacts are in electrical communication with different metal combs. In this manner, upon testing for electrical continuity, an electrical current passing from the first metal comb to the second metal comb indicates an electrical defect existing between adjacent metal contacts.

    摘要翻译： 本发明涉及一种在半导体器件内的第一金属级使用这种测试结构检测相邻金属触点之间的电气缺陷的测试结构和方法。 测试结构包括双重第一金属级梳结构，每个具有与位于半导体中的触点直接电连通的延伸线。 第一金属梳的延伸线与第二金属梳上的延伸线交错，使得相邻的金属触点与不同的金属梳电连接。 以这种方式，在测试电连续性时，从第一金属梳到第二金属梳的电​​流表示存在于相邻的金属触点之间的电缺陷。