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    Balanced P-LRU tree for a “multiple of 3” number of ways cache
    1.
    发明授权
    Balanced P-LRU tree for a “multiple of 3” number of ways cache 有权
    平衡的P-LRU树为“多个3”的缓存方式

    公开(公告)号：US09348766B2

    公开(公告)日：2016-05-24

    申请号：US13994690

    申请日：2011-12-21

    申请人： Adi Basel ,  Gur Hildesheim ,  Shlomo Raikin ,  Robert Chappell ,  Ho-Seop Kim ,  Rohit Bhatia

    发明人： Adi Basel ,  Gur Hildesheim ,  Shlomo Raikin ,  Robert Chappell ,  Ho-Seop Kim ,  Rohit Bhatia

    IPC分类号： G06F13/00 ,  G06F12/12 ,  G06F3/06 ,  G06F12/00 ,  G06F12/08

    CPC分类号： G06F12/122 ,  G06F3/0604 ,  G06F12/00 ,  G06F12/0842 ,  G06F12/0864 ,  G06F12/124 ,  G06F12/125

    摘要： In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing a balanced P-LRU tree for a “multiple of 3” number of ways cache. For example, in one embodiment, such means may include an integrated circuit having a cache and a plurality of ways. In such an embodiment the plurality of ways include a quantity that is a multiple of three and not a power of two, and further in which the plurality of ways are organized into a plurality of pairs. In such an embodiment, means further include a single bit for each of the plurality of pairs, in which each single bit is to operate as an intermediate level decision node representing the associated pair of ways and a root level decision node having exactly two individual bits to point to one of the single bits to operate as the intermediate level decision nodes representing an associated pair of ways. In this exemplary embodiment, the total number of bits is N−1, wherein N is the total number of ways in the plurality of ways. Alternative structures are also presented for full LRU implementation, a “multiple of 5” number of cache ways, and variations of the “multiple of 3” number of cache ways.

    摘要翻译： 根据本文公开的实施例，提供了用于实现用于“3”倍的方式缓存的平衡P-LRU树的方法，系统，机制，技术和装置。 例如，在一个实施例中，这种装置可以包括具有高速缓存和多个方式的集成电路。 在这样的实施例中，多个方式包括量是三的倍数而不是二的幂，并且其中多个方式被组织成多对。 在这种实施例中，装置还包括用于多个对中的每一对的单个比特，其中每个单个比特将用作表示相关联的一对路由的中间级别决策节点，以及具有正好两个单独比特的根级别决策节点 指向要作为表示相关联的方式的中间级决策节点操作的单个位之一。 在该示例性实施例中，总数是N-1，其中N是多个方式的总路数。 还提供了替代结构，用于完整的LRU实现，“多路复用5”缓存方式，以及“3”倍数缓存方式的变化。

    BALANCED P-LRU TREE FOR A
    2.
    发明申请
    BALANCED P-LRU TREE FOR A "MULTIPLE OF 3" NUMBER OF WAYS CACHE 有权
    平衡P-LRU树为“多个3”的方式快速访问

    公开(公告)号：US20140215161A1

    公开(公告)日：2014-07-31

    申请号：US13994690

    申请日：2011-12-21

    申请人： Adi Basel ,  Gur Hildeshem ,  Shlomo Raikin ,  Robert Chappell ,  Ho-Seop Kim ,  Rohit Bhatia

    发明人： Adi Basel ,  Gur Hildeshem ,  Shlomo Raikin ,  Robert Chappell ,  Ho-Seop Kim ,  Rohit Bhatia

    IPC分类号： G06F12/12

    CPC分类号： G06F12/122 ,  G06F3/0604 ,  G06F12/00 ,  G06F12/0842 ,  G06F12/0864 ,  G06F12/124 ,  G06F12/125

    摘要： In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing a balanced P-LRU tree for a “multiple of 3” number of ways cache. For example, in one embodiment, such means may include an integrated circuit having a cache and a plurality of ways. In such an embodiment the plurality of ways include a quantity that is a multiple of three and not a power of two, and further in which the plurality of ways are organized into a plurality of pairs. In such an embodiment, means further include a single bit for each of the plurality of pairs, in which each single bit is to operate as an intermediate level decision node representing the associated pair of ways and a root level decision node having exactly two individual bits to point to one of the single bits to operate as the intermediate level decision nodes representing an associated pair of ways. In this exemplary embodiment, the total number of bits is N−1, wherein N is the total number of ways in the plurality of ways. Alternative structures are also presented for full LRU implementation, a “multiple of 5” number of cache ways, and variations of the “multiple of 3” number of cache ways.

    摘要翻译： 根据本文公开的实施例，提供了用于实现用于“3”倍的方式缓存的平衡P-LRU树的方法，系统，机制，技术和装置。 例如，在一个实施例中，这种装置可以包括具有高速缓存和多个方式的集成电路。 在这样的实施例中，多个方式包括量是三的倍数，而不是二的幂，并且其中多个方式被组织成多对。 在这样的实施例中，装置还包括用于多个对中的每一对的单个位，其中每个单个位将用作表示相关联的方式的中间级决策节点，以及具有正好两个单独位的根级决策节点 指向要作为表示相关联的方式的中间级决策节点操作的单个位之一。 在该示例性实施例中，总数是N-1，其中N是多个方式的总路数。 还提供了替代结构，用于完整的LRU实现，“多路复用5”缓存方式，以及“3”倍数缓存方式的变化。

    Miter attachment
    4.
    发明授权
    Miter attachment 失效
    斜角附件

    公开(公告)号：US4079648A

    公开(公告)日：1978-03-21

    申请号：US733535

    申请日：1976-10-18

    申请人： Robert Chappell

    发明人： Robert Chappell

    IPC分类号： B23D59/00 ,  B27B5/18 ,  B27G5/02 ,  B27B9/04

    CPC分类号： B23D59/007 ,  B27B5/185 ,  B27G5/023 ,  Y10T83/7693 ,  Y10T83/773 ,  Y10T83/7755 ,  Y10T83/7788

    摘要： A miter attachment for use with a portable electric circular saw. This miter attachment has a smooth upper platform secured to rails positioned at 90.degree., and at 45.degree. right and left which are also secured to the base. A portable saw is placed on the upper platform with the circular blade in the marked pre-cut saw groove for true miter cutting. The saw shoe is fixed in position by clamps and the user releases the elevation knob on the saw, allowing it to move freely up and down on a pin hinged to the saw shoe. A plunge cut is achieved as the saw is lowered and the blade passes through the workpiece, placed and held against the rail between the upper platform and the base.

    摘要翻译： 与便携式电动圆锯一起使用的斜切附件。 该斜角附件具有平滑的上部平台，固定到位于90°的轨道上，并且在左右45度处固定，也固定到基座。 将便携式锯放置在上平台上，圆形刀片在标明的预切割锯槽中，用于真正的斜切切割。 锯条通过夹具固定在适当的位置，用户释放锯上的升降旋钮，使其能够在铰链到锯条上的销上上下自由移动。 当锯下降并且刀片穿过工件时，实现切入切口，并将其放置并保持抵靠上部平台和底座之间的轨道。