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公开(公告)号：US12068215B2
公开(公告)日：2024-08-20
申请号：US18152022
申请日：2023-01-09
发明人： David A. Roberts , Greg Sadowski , Steven Raasch
IPC分类号： H01L23/34 , G05B15/02 , G06F1/20 , H01L25/065
CPC分类号： H01L23/34 , G05B15/02 , G06F1/20 , H01L25/0657 , H01L2225/06589
摘要： Exemplary embodiments provide thermal wear spreading among a plurality of thermal die regions in an integrated circuit or among dies by using die region wear-out data that represents a cumulative amount of time each of a number of thermal die regions in one or more dies has spent at a particular temperature level. In one example, die region wear-out data is stored in persistent memory and is accrued over a life of each respective thermal region so that a long term monitoring of temperature levels in the various die regions is used to spread thermal wear among the thermal die regions. In one example, spreading thermal wear is done by controlling task execution such as thread execution among one or more processing cores, dies and/or data access operations for a memory.
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公开(公告)号：US11275558B2
公开(公告)日：2022-03-15
申请号：US16206879
申请日：2018-11-30
发明人： David A. Roberts
IPC分类号： G06F7/22 , G06F16/901 , G06N3/04
摘要： An electronic device including a neural network processor and a presorter is described. The presorter determines a sorted order to be used by the neural network processor for processing a set of instances of input data through the neural network, the determining including rearranging an initial order of some or all of the instances of input data so that instances of input data having specified similarities among the some or all of the instances of input data are located nearer to one another in the sorted order. The presorter provides, to the neural network processor, the sorted order to be used for controlling an order in which instances of input data from among the set of instances of input data are processed through the neural network. A controller in the electronic device adjusts operation of the presorter based on efficiencies of the presorter and the neural network processor.
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公开(公告)号：US11237972B2
公开(公告)日：2022-02-01
申请号：US15857837
申请日：2017-12-29
发明人： David A. Roberts
IPC分类号： G06F12/08 , G06F12/0846 , G06F12/0862 , G06F12/0815
摘要： A method and apparatus physically partitions clean and dirty cache lines into separate memory partitions, such as one or more banks, so that during low power operation, a cache memory controller reduces power consumption of the cache memory containing the clean only data. The cache memory controller controls a refresh operation so that a data refresh does not occur for the clean data only banks or the refresh rate is reduced for the clean data only banks. Partitions that store dirty data can also store clean data; however, other partitions are designated for storing only clean data so that the partitions can have their refresh rate reduced or refresh stopped for periods of time. When multiple DRAM dies or packages are employed, the partition can occur on a die or package level as opposed to a bank level within a die.
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公开(公告)号：US11055150B2
公开(公告)日：2021-07-06
申请号：US15952143
申请日：2018-04-12
摘要： A thread holding a lock notifies a sleeping thread that is waiting on the lock that the lock holding thread is “about” to release the lock. In response to the notification, the waiting thread is woken up. While the waiting thread is woken up, the lock holding thread completes other operations prior to actually releasing the lock and then releases the lock. The notification to the waiting thread hides latency associated with waking up the waiting thread by allowing operations that wake up the waiting thread to occur while the lock holding thread is performing the other operations prior to releasing the thread.
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公开(公告)号：US10862809B2
公开(公告)日：2020-12-08
申请号：US15600048
申请日：2017-05-19
发明人： David A. Roberts
IPC分类号： H04L12/833 , H04L12/46 , H04L12/851 , H04L12/28 , H04L12/723
摘要： The described embodiments include an electronic device that handles network packets. During operation, the electronic device receives a carrier packet, the carrier packet that includes a tunneled packet in a payload of the carrier packet, wherein the tunneled packet includes a packet priority of the tunneled packet and the carrier packet includes a packet priority of the carrier packet. The electronic device then updates the packet priority of the carrier packet based on the packet priority of the tunneled packet.
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公开(公告)号：US20200081864A1
公开(公告)日：2020-03-12
申请号：US16127607
申请日：2018-09-11
发明人： David A. Roberts , Shenghsun Cho
IPC分类号： G06F15/173 , G06F13/16 , G06F13/40 , G06F12/0862
摘要： A system is described that performs memory access operations. The system includes a processor in a first node, a memory in a second node, a communication interconnect coupled to the processor and the memory, and an interconnect controller in the first node coupled between the processor and the communication interconnect. Upon executing a multi-line memory access instruction, the processor prepares a memory access operation for accessing, in the memory, a block of data including at least some of each of at least two lines of data. The processor then causes the interconnect controller to use a single remote direct memory access memory transfer to perform the memory access operation for the block of data via the communication interconnect.
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公开(公告)号：US10431305B2
公开(公告)日：2019-10-01
申请号：US15841997
申请日：2017-12-14
IPC分类号： G11C16/10 , G11C14/00 , G11C7/10 , H01L27/108
摘要： A high-performance on-module caching architecture for hybrid memory modules is provided. A hybrid memory module includes a cache controller, a first volatile memory coupled to the cache controller, a first multiplexing data buffer coupled to the first volatile memory and the cache controller, and a first non-volatile memory coupled to the first multiplexing data buffer and the cache controller, wherein the first multiplexing data buffer multiplexes data between the first volatile memory and the first non-volatile memory and wherein the cache controller enables a tag checking operation to occur in parallel with a data movement operation. The hybrid memory module includes a volatile memory tag unit coupled to the cache controller, wherein the volatile memory tag unit includes a line connection that allows the cache controller to store a plurality of tags in the volatile memory tag unit and retrieve the plurality of tags from the volatile memory tag unit.
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公开(公告)号：US20190205492A1
公开(公告)日：2019-07-04
申请号：US15859156
申请日：2017-12-29
发明人： David A. Roberts , Dean Gonzales
IPC分类号： G06F17/50
摘要： An electronic device includes a first integrated circuit chip including a processing functional block, and a second integrated circuit chip including an input-output (IO) functional block. The IO functional block performs one or more IO processing operations on behalf of the processing functional block in the first integrated circuit chip. The first integrated circuit chip lacks at least some elements of the IO functional block, so that the processing functional block is unable to perform corresponding IO operations without the IO functional block.
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公开(公告)号：US10331537B2
公开(公告)日：2019-06-25
申请号：US15389573
申请日：2016-12-23
发明人： Manish Gupta , Vilas Sridharan , David A. Roberts
IPC分类号： G06F11/00 , G06F11/34 , G06F12/0891
摘要： Described herein are waterfall counters and an application to architectural vulnerability factor (AVF) estimation. Waterfall counters count events that are generated at event generation logic. The waterfall counters are a combination of small, fast counters local to the event generation logic, and larger, global counters in fast memory. The local counters can be saturation or oscillation counters. When a local counter is saturated or evicted, the value from the local counter is added to the global counter. This addition can be done using logic local to the local or global counter. The waterfall counters provide a full-accuracy event count without the high bandwidth that is needed to maintain the global counters. An AVF estimation can be determined based on ratios from counts of read events, write events, and total events using the waterfall counters.
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公开(公告)号：US10268416B2
公开(公告)日：2019-04-23
申请号：US14924881
申请日：2015-10-28
发明人： Nuwan Jayasena , David A. Roberts
IPC分类号： G06F3/06 , G06F12/08 , G06F12/0817
摘要： A memory-to-memory copy operation control system includes a processor configured to receive an instruction to perform a memory-to-memory copy operation and a memory module network in communication with the processor. The memory module network has a plurality of memory modules that include a proximal memory module in direct communication with the processor and one or more additional memory modules in communication with the processor via the proximal memory module. The system also includes a memory controller in communication with the processor and the network of memory modules. The processor is configured to issue a first command causing data to be copied from a first memory module to a second memory module without sending the data to the processor or the memory controller.
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