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公开(公告)号：US10235290B2
公开(公告)日：2019-03-19
申请号：US14752408
申请日：2015-06-26
Applicant: Advanced Micro Devices, Inc.
Inventor： Sergey Blagodurov , Gabriel H. Loh , Mitesh R. Meswani
IPC: G06F12/02 , G06F12/0811 , G06F12/0897 , G06F12/1027
Abstract: Systems, apparatuses, and methods for sorting memory pages in a multi-level heterogeneous memory architecture. The system may classify pages into a first “hot” category or a second “cold” category. The system may attempt to place the “hot” pages into the memory level(s) closest to the systems' processor cores. The system may track parameters associated with each page, with the parameters including number of accesses, types of accesses, power consumed per access, temperature, wearability, and/or other parameters. Based on these parameters, the system may generate a score for each page. Then, the system may compare the score of each page to a threshold. If the score of a given page is greater than the threshold, the given page may be designated as “hot”. If the score of the given page is less than the threshold, the given page may be designated as “cold”.
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公开(公告)号：US09727241B2
公开(公告)日：2017-08-08
申请号：US14616058
申请日：2015-02-06
Applicant: Advanced Micro Devices, Inc.
Inventor： Gabriel H. Loh , David A. Roberts , Mitesh R. Meswani , Mark R. Nutter , John R. Slice , Prashant Nair , Michael Ignatowski
IPC: G06F12/10 , G06F3/06 , G06F12/0893 , G06F12/1045
CPC classification number: G06F3/0604 , G06F3/0653 , G06F3/0673 , G06F12/0893 , G06F12/1027 , G06F12/1045 , G06F2212/60 , G06F2212/68
Abstract: A processor maintains a count of accesses to each memory page. When the accesses to a memory page exceed a threshold amount for that memory page, the processor sets an indicator for the page. Based on the indicators for the memory pages, the processor manages data at one or more levels of the processor's memory hierarchy.
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公开(公告)号：US20190286362A1
公开(公告)日：2019-09-19
申请号：US16432391
申请日：2019-06-05
Applicant: Advanced Micro Devices, Inc.
Inventor： Arkaprava Basu , Mitesh R. Meswani , Dibakar Gope , Sooraj Puthoor
Abstract: A processing apparatus is provided that includes NVRAM and one or more processors configured to process a first set and a second set of instructions according to a hierarchical processing scope and process a scoped persistence barrier residing in the program after the first instruction set and before the second instruction set. The barrier includes an instruction to cause first data to persist in the NVRAM before second data persists in the NVRAM. The first data results from execution of each of the first set of instructions processed according to the one hierarchical processing scope. The second data results from execution of each of the second set of instructions processed according to the one hierarchical processing scope. The processing apparatus also includes a controller configured to cause the first data to persist in the NVRAM before the second data persists in the NVRAM based on the scoped persistence barrier.
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公开(公告)号：US09983655B2
公开(公告)日：2018-05-29
申请号：US14963352
申请日：2015-12-09
Applicant: Advanced Micro Devices, Inc.
Inventor： Mitesh R. Meswani , David A. Roberts , Dmitri Yudanov , Arkaprava Basu , Sergey Blagodurov
CPC classification number: G06F1/3243 , G06F9/3885
Abstract: A method and apparatus for performing inter-lane power management includes de-energizing one or more execution lanes upon a determination that the one or more execution lanes are to be predicated. Energy from the predicated execution lanes is redistributed to one or more active execution lanes.
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5.发明申请公开(公告)号：US20170277441A1
公开(公告)日：2017-09-28
申请号：US15331270
申请日：2016-10-21
Applicant: Advanced Micro Devices, Inc.
Inventor： Manish Gupta , David A. Roberts , Mitesh R. Meswani , Vilas Sridharan , Steven Raasch , Daniel I. Lowell
IPC: G06F3/06
CPC classification number: G06F12/02
Abstract: Techniques for selecting one of a plurality of heterogeneous memory units for placement of blocks of data (e.g., memory pages), based on both reliability and performance, are disclosed. A “cost” for each data block/memory unit combination is determined, based on the frequency of access of the data block, the latency of the memory unit, and, optionally, an architectural vulnerability factor (which represents the level of exposure of a particular memory data value to memory faults such as bit flips). A memory unit is selected for the data block for which the determined cost is the lowest, out of all memory units considered, and the data block is placed into that memory unit.
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Patent Agency Ranking
公开(公告)号：US20160378655A1
公开(公告)日：2016-12-29
申请号：US14752408
申请日：2015-06-26
Applicant: Advanced Micro Devices, Inc.
Inventor： Sergey Blagodurov , Gabriel H. Loh , Mitesh R. Meswani
IPC: G06F12/08
CPC classification number: G06F12/0811 , G06F12/0897 , G06F12/1027 , Y02D10/13
Abstract: Systems, apparatuses, and methods for sorting memory pages in a multi-level heterogeneous memory architecture. The system may classify pages into a first “hot” category or a second “cold” category. The system may attempt to place the “hot” pages into the memory level(s) closest to the systems' processor cores. The system may track parameters associated with each page, with the parameters including number of accesses, types of accesses, power consumed per access, temperature, wearability, and/or other parameters. Based on these parameters, the system may generate a score for each page. Then, the system may compare the score of each page to a threshold. If the score of a given page is greater than the threshold, the given page may be designated as “hot”. If the score of the given page is less than the threshold, the given page may be designated as “cold”.
Abstract translation: 用于在多级异构存储器架构中分类存储器页面的系统，装置和方法。 系统可以将页面分类为第一个“热”类别或第二个“冷”类别。 系统可能会尝试将“热”页放置在最接近系统处理器内核的存储器级中。 系统可以跟踪与每个页面相关联的参数，其中参数包括访问次数，访问类型，每次访问消耗的功率，温度，耐磨性和/或其他参数。 基于这些参数，系统可以为每个页面生成分数。 然后，系统可以将每个页面的分数与阈值进行比较。 如果给定页面的分数大于阈值，则给定页面可能被指定为“热”。 如果给定页面的分数小于阈值，则给定的页面可以被指定为“冷”。
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公开(公告)号：US11573724B2
公开(公告)日：2023-02-07
申请号：US16432391
申请日：2019-06-05
Applicant: Advanced Micro Devices, Inc.
Inventor： Arkaprava Basu , Mitesh R. Meswani , Dibakar Gope , Sooraj Puthoor
Abstract: A processing apparatus is provided that includes NVRAM and one or more processors configured to process a first set and a second set of instructions according to a hierarchical processing scope and process a scoped persistence barrier residing in the program after the first instruction set and before the second instruction set. The barrier includes an instruction to cause first data to persist in the NVRAM before second data persists in the NVRAM. The first data results from execution of each of the first set of instructions processed according to the one hierarchical processing scope. The second data results from execution of each of the second set of instructions processed according to the one hierarchical processing scope. The processing apparatus also includes a controller configured to cause the first data to persist in the NVRAM before the second data persists in the NVRAM based on the scoped persistence barrier.
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公开(公告)号：US10324650B2
公开(公告)日：2019-06-18
申请号：US15274777
申请日：2016-09-23
Applicant: Advanced Micro Devices, Inc.
Inventor： Arkaprava Basu , Mitesh R. Meswani , Dibakar Gope , Sooraj Puthoor
Abstract: A processing apparatus is provided that includes NVRAM and one or more processors configured to process a first set and a second set of instructions according to a hierarchical processing scope and process a scoped persistence barrier residing in the program after the first instruction set and before the second instruction set. The barrier includes an instruction to cause first data to persist in the NVRAM before second data persists in the NVRAM. The first data results from execution of each of the first set of instructions processed according to the one hierarchical processing scope. The second data results from execution of each of the second set of instructions processed according to the one hierarchical processing scope. The processing apparatus also includes a controller configured to cause the first data to persist in the NVRAM before the second data persists in the NVRAM based on the scoped persistence barrier.
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公开(公告)号：US20170083474A1
公开(公告)日：2017-03-23
申请号：US14862011
申请日：2015-09-22
Applicant: Advanced Micro Devices, Inc.
Inventor： Mitesh R. Meswani , David A. Roberts , Yasuko Eckert , Kapil Dev , John Kalamatianos , Indrani Paul
CPC classification number: G06F13/4234 , G06F12/084 , G06F12/0862 , G06F13/18 , G06F2212/314 , G06F2212/603 , Y02D10/13 , Y02D10/14 , Y02D10/151
Abstract: A plurality of first controllers operate according to a plurality of access protocols to control a plurality of memory modules. A second controller receives access requests that target the plurality of memory modules and selectively provides the access requests and control information to the plurality of first controllers based on physical addresses in the access requests. The second controller generates the control information for the first controllers based on statistical representations of the access requests to the plurality of memory modules.
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公开(公告)号：US20170083444A1
公开(公告)日：2017-03-23
申请号：US14862030
申请日：2015-09-22
Applicant: Advanced Micro Devices, Inc.
Inventor： Kapil Dev , Mitesh R. Meswani , David A. Roberts , Yasuko Eckert , Indrani Paul , John Kalamatianos
CPC classification number: G06F12/0871 , G06F12/0804 , G06F12/0811 , G06F12/121 , G06F2212/1024 , G06F2212/214 , G06F2212/2515 , G06F2212/502 , G06F2212/601
Abstract: A cache controller to configure a portion of a first memory as cache for a second memory responsive to an indicator of locality of memory access requests to the second memory. The indicator of locality determines a probability that a location of a memory access request to the second memory is predictable based upon at least one previous memory access request. The cache controller may determine a size of the cache based on a value of the indicator of locality or modify the size of the cache in response to changes in the value of the indicator of locality.
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