公开(公告)号：US20210327796A1

公开(公告)日：2021-10-21

申请号：US16853396

申请日：2020-04-20

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Tang-Yuan CHEN ,  Chih-Pin HUNG

IPC分类号： H01L23/498 ,  H01L23/538 ,  H01L23/00

摘要： A wiring structure is provided. The wiring structure includes an upper redistribution structure, a lower redistribution structure, a conductive structure, an upper bonding layer and a lower bonding layer. The conductive structure is disposed between and electrically connected to the upper redistribution structure and the lower redistribution structure. The upper bonding layer is disposed between the upper redistribution structure and the conductive structure to bond the upper redistribution structure and the conductive structure together. The lower bonding layer is disposed between the lower redistribution structure and the conductive structure to bond the lower redistribution structure and the conductive structure together.

公开(公告)号：US20200211863A1

公开(公告)日：2020-07-02

申请号：US16813364

申请日：2020-03-09

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Ying-Xu LU ,  Tang-Yuan CHEN ,  Jin-Yuan LAI ,  Tse-Chuan CHOU ,  Meng-Kai SHIH ,  Shin-Luh TARNG

IPC分类号： H01L21/56 ,  H01L23/498 ,  H01L23/00 ,  H01L23/13

摘要： The present disclosure relates to a semiconductor device package including a substrate, a semiconductor device and an underfill. The substrate has a first surface and a second surface angled with respect to the first surface. The semiconductor device is mounted on the first surface of the substrate and has a first surface facing the first surface of the substrate and a second surface angled with respect to the first surface of the substrate. The underfill is disposed between the first surface of the semiconductor device and the first surface of the substrate. The second surface of the substrate is located in the substrate and external to a vertical projection of the semiconductor device on the first surface of the substrate. A distance between the second surface of the substrate and an extension of the second surface of the semiconductor device on the first surface of the substrate is less than or equal to twice a distance between the first surface of the semiconductor device and the first surface of the substrate. The second surface of the substrate extends along at least three sides of the semiconductor device.

公开(公告)号：US20190074264A1

公开(公告)日：2019-03-07

申请号：US15698451

申请日：2017-09-07

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Bo-Syun CHEN ,  Tang-Yuan CHEN ,  Yu-Chang CHEN ,  Jin-Feng YANG ,  Chin-Li KAO ,  Meng-Kai SHIH

IPC分类号： H01L25/065 ,  H01L25/00

CPC分类号： H01L25/0657 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/13 ,  H01L23/3677 ,  H01L23/49811 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/29347 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/83192 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06537 ,  H01L2225/06558 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2224/81

摘要： A semiconductor package structure includes a first substrate, at least one first semiconductor element and a second substrate. The first semiconductor element is attached to the first substrate. The second substrate defines a cavity and includes a plurality of thermal vias. One end of each of the thermal vias is exposed in the cavity, and the first semiconductor element is disposed within the cavity and thermally connected to the thermal vias.

公开(公告)号：US20180358238A1

公开(公告)日：2018-12-13

申请号：US15619415

申请日：2017-06-09

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Jin-Yuan LAI ,  Tang-Yuan CHEN ,  Ying-Xu LU ,  Dao-Long CHEN ,  Kwang-Lung LIN ,  Chih-Pin HUNG ,  Tse-Chuan CHOU ,  Ming-Hung CHEN ,  Chi-Hung PAN

IPC分类号： H01L21/56 ,  H01L23/00 ,  H01L21/48 ,  H01L23/498

CPC分类号： H01L21/563 ,  H01L21/481 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83143 ,  H01L2224/83493 ,  H01L2224/83888 ,  H01L2224/83889 ,  H01L2924/01006

摘要： The present disclosure relates to a semiconductor device package comprising a substrate, a semiconductor device, and a underfill. The substrate includes a top surface defining a mounting area, and a barrier section on the top surface and adjacent to the mounting area. The semiconductor device is mounted on the mounting area of the substrate. The underfill is disposed between the semiconductor device and the mounting area and the barrier section of the substrate. A contact angle between a surface of the underfill and the barrier section is greater than or equal to about 90 degrees.

公开(公告)号：US20190287947A1

公开(公告)日：2019-09-19

申请号：US16434008

申请日：2019-06-06

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Bo-Syun CHEN ,  Tang-Yuan CHEN ,  Yu-Chang CHEN ,  Jin-Feng YANG ,  Chin-Li KAO ,  Meng-Kai SHIH

IPC分类号： H01L25/065 ,  H01L23/552 ,  H01L25/00 ,  H01L23/13 ,  H01L23/498 ,  H01L21/48 ,  H01L23/367 ,  H01L23/538

摘要： A semiconductor package structure includes: (1) a first substrate; (2) at least one first semiconductor element attached to the first substrate; and (3) a second substrate including a plurality of thermal vias and a plurality of conductive vias, wherein one end of each of the thermal vias directly contacts the first semiconductor element.

公开(公告)号：US20160300782A1

公开(公告)日：2016-10-13

申请号：US14685529

申请日：2015-04-13

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Tang-Yuan CHEN ,  Chin-Li KAO ,  Kuo-Hua CHEN ,  Ming-Hung CHEN ,  Dao-Long CHEN

IPC分类号： H01L23/495 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L23/49548 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49568 ,  H01L23/49582 ,  H01L23/49816 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/20 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/32245 ,  H01L2224/32502 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/83801 ,  H01L2224/83805 ,  H01L2224/92244 ,  H01L2924/15153 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/00014

摘要： The present disclosure relates to a semiconductor package structure and a method for manufacturing the same. The semiconductor package structure includes a leadframe and a semiconductor die. The leadframe includes a main portion and a protrusion portion. The semiconductor die is bonded to a first surface of the main portion. The protrusion portion protrudes from a second surface of the main portion. The position of the protrusion portion corresponds to the position of the semiconductor die.

摘要翻译： 本公开涉及一种半导体封装结构及其制造方法。 半导体封装结构包括引线框和半导体管芯。 引线框架包括主体部分和突出部分。 半导体管芯结合到主要部分的第一表面。 突出部分从主体部分的第二表面突出。 突起部分的位置对应于半导体管芯的位置。

公开(公告)号：US20160240481A1

公开(公告)日：2016-08-18

申请号：US14624331

申请日：2015-02-17

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Chia-Ching CHEN ,  Chin-Li KAO ,  Hung-Jen CHANG ,  Tang-Yuan CHEN ,  Wei-Hong LAI

IPC分类号： H01L23/538 ,  H05K1/11 ,  H01L21/683 ,  H01L23/498 ,  H01L21/48

CPC分类号： H01L23/5389 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L2221/68345 ,  H01L2224/16227 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15331 ,  H05K3/205 ,  H05K2201/10378

摘要： Described herein are interposer substrate designs for warpage control, semiconductor structures including said interposer substrates, and fabricating processes thereof. An interposer substrate defines a cavity and further includes a reinforcement structure, wherein the reinforcement structure is used to control warpage of the semiconductor package structure.

摘要翻译： 这里描述了用于翘曲控制的插入式衬底设计，包括所述插入器衬底的半导体结构及其制造工艺。 插入器基板限定空腔并且还包括加强结构，其中加强结构用于控制半导体封装结构的翘曲。

公开(公告)号：US20210288024A1

公开(公告)日：2021-09-16

申请号：US17322764

申请日：2021-05-17

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Tang-Yuan CHEN ,  Meng-Kai SHIH ,  Teck-Chong LEE ,  Shin-Luh TARNG ,  Chih-Pin HUNG

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/528 ,  H01L21/56

摘要： A semiconductor device package includes a first conductive layer, a second conductive layer and a third conductive layer. The first conductive layer has a first pitch. The second conductive layer has a second pitch and is arranged at two different sides of the first conductive layer. The third conductive layer has a third pitch and is disposed above the first conductive layer and the second conductive layer. The third conductive layer is electrically connected to the first conductive layer. The first pitch is smaller than the third pitch, and the third pitch is smaller than the second pitch.

公开(公告)号：US20210280744A1

公开(公告)日：2021-09-09

申请号：US16809500

申请日：2020-03-04

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Tang-Yuan CHEN ,  Meng-Wei HSIEH ,  Cheng-Yuan KUNG

IPC分类号： H01L33/14 ,  H01L33/00

摘要： A semiconductor device package includes a carrier, an emitting element and a first package body. The carrier includes a first surface and a second surface opposite to the first surface. The emitting element is disposed on the first surface of the carrier. The first package body is disposed over the first surface of the carrier and spaced apart from the first surface of the carrier.

公开(公告)号：US20200381338A1

公开(公告)日：2020-12-03

申请号：US16430260

申请日：2019-06-03

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Tang-Yuan CHEN ,  Yuan Tzuo LUO ,  Shao-Cheng YEN ,  Meng-Kai SHIH ,  Chih-Pin HUNG

IPC分类号： H01L23/433 ,  H01L23/31 ,  H01L21/56

摘要： A semiconductor device package includes a carrier, an electronic component, a package body and a ring structure. The electronic component is disposed on the carrier. The electronic component has a side surface. The package body is disposed on the carrier. The package body exposes at least a portion of the side surface of the electronic component. The ring structure is disposed on the package body and surrounds the portion of the side surface of the electronic component exposed from the package body.