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公开(公告)号：US12183683B2
公开(公告)日：2024-12-31
申请号：US17501952
申请日：2021-10-14
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor： Wei-Jen Wang , Po-Jen Cheng , Fu-Yuan Chen
IPC: H01L23/538 , H01L21/48 , H01L25/065 , H01L25/18 , H01L23/00 , H01L23/31
Abstract: An electronic package structure includes an electronic structure, a wiring structure, an electrical contact and a support layer. The wiring structure is located over the electronic structure. The electrical contact connects the wiring structure and the electronic structure. The support layer is disposed around the electrical contact and has a surface facing the electrical contact. The surface includes at least one inflection point in a cross-sectional view.
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公开(公告)号：US11961808B2
公开(公告)日：2024-04-16
申请号：US17501953
申请日：2021-10-14
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor： Wei-Jen Wang , Po-Jen Cheng , Fu-Yuan Chen , Yi-Hsin Cheng
IPC: H01L23/498 , H01L23/00 , H01L23/538
CPC classification number: H01L23/562 , H01L23/49811 , H01L23/5386 , H01L24/14
Abstract: At least some embodiments of the present disclosure relate to an electronic package structure. The electronic package structure includes an electronic structure, a wiring structure disposed over the electronic structure, a bonding element connecting the wiring structure and the electronic structure, and a reinforcement element attached to the wiring structure. An elevation difference between a highest point and a lowest point of a surface of the wiring structure facing the electronic structure is less than a height of the bonding element.
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公开(公告)号：US12218094B2
公开(公告)日：2025-02-04
申请号：US18610185
申请日：2024-03-19
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor： Wei-Jen Wang , Yi Dao Wang , Tung Yao Lin
IPC: H01L23/00 , H01L23/498
Abstract: An electronic package structure and a method for manufacturing the same are provided. The electronic package structure includes a first electronic component, a second electronic component, an interconnection element, an insulation layer, and an encapsulant. The second electronic component is disposed adjacent to the first electronic component. The interconnection element is disposed between the first electronic component and the second electronic component. The insulation layer is disposed between the first electronic component and the second electronic component and has a side surface and a top surface connecting to the side surface. The encapsulant surrounds the interconnection element and at least partially covers the top surface of the insulation layer and has an extended portion in contact with the side surface of the insulation layer.
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公开(公告)号：US10229859B2
公开(公告)日：2019-03-12
申请号：US15654549
申请日：2017-07-19
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor： Wei-Jen Wang
Abstract: At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package includes a first substrate, an electrical component disposed on the first substrate, a second substrate disposed over the electrical component, an adhesive layer, a spacer, and an encapsulation layer. The adhesive layer is disposed between the electrical component and the second substrate. The spacer directly contacts both the adhesive layer and the second substrate. The encapsulation layer is disposed between the first substrate and the second substrate.
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公开(公告)号：US11935855B2
公开(公告)日：2024-03-19
申请号：US17535407
申请日：2021-11-24
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor： Wei-Jen Wang , Yi Dao Wang , Tung Yao Lin
IPC: H01L23/00 , H01L23/498
CPC classification number: H01L24/16 , H01L23/49822 , H01L24/73 , H01L24/81 , H01L2224/10122 , H01L2224/10145 , H01L2224/16145 , H01L2224/16227 , H01L2224/73204 , H01L2224/81203 , H01L2224/81224
Abstract: An electronic package structure and a method for manufacturing the same are provided. The electronic package structure includes a first electronic component, a second electronic component, an interconnection element, an insulation layer, and an encapsulant. The second electronic component is disposed adjacent to the first electronic component. The interconnection element is disposed between the first electronic component and the second electronic component. The insulation layer is disposed between the first electronic component and the second electronic component and has a side surface and a top surface connecting to the side surface. The encapsulant surrounds the interconnection element and at least partially covers the top surface of the insulation layer and has an extended portion in contact with the side surface of the insulation layer.
