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    Low Latency High Bandwidth CDR Architecture
    1.
    发明申请
    Low Latency High Bandwidth CDR Architecture 有权
    低延迟高带宽CDR体系结构

    公开(公告)号：US20120328063A1

    公开(公告)日：2012-12-27

    申请号：US13168861

    申请日：2011-06-24

    Applicant: Anand Jitendra Vasani ,  Jun Cao ,  Afshin Momtaz

    Inventor： Anand Jitendra Vasani ,  Jun Cao ,  Afshin Momtaz

    IPC: H04L7/02

    CPC classification number: H04L7/0079 ,  H03L7/0812 ,  H04L7/033

    Abstract: Provided is a low latency high bandwidth clock and data recovery (CDR) system. For example, there is a low latency high bandwidth CDR system including a demultiplexer configured to convert a high frequency input datastream to a low frequency output datastream according to a first latency and a phase error processor at least partially embedded into the demultiplexer and configured to determine a datastream phase error of the high frequency input datastream according to a second latency. The embedded phase error processor allows a portion of a total latency of the CDR system due to the demultiplexer and the phase error processor to be less than a sum of the first and second latencies.

    Abstract translation: 提供了低延迟高带宽时钟和数据恢复（CDR）系统。 例如，存在低延迟高带宽CDR系统，其包括解复用器，其被配置为根据第一等待时间将高频输入数据流转换为低频输出数据流，并且相位误差处理器至少部分地被嵌入到解复用器中并且被配置为确定 根据第二等待时间，高频输入数据流的数据流相位误差。 嵌入式相位误差处理器允许由于解复用器和相位误差处理器而导致的CDR系统的总等待时间的一部分小于第一和第二延迟的和。

    Distributed threshold adjustment for high speed receivers
    2.
    发明授权
    Distributed threshold adjustment for high speed receivers 有权
    高速接收机的分布式阈值调整

    公开(公告)号：US08077060B2

    公开(公告)日：2011-12-13

    申请号：US12582442

    申请日：2009-10-20

    Applicant: Afshin Momtaz ,  Namik K. Kocaman ,  Bharath Raghavan

    Inventor： Afshin Momtaz ,  Namik K. Kocaman ,  Bharath Raghavan

    IPC: H03M7/00

    CPC classification number: H03F3/45475 ,  H03F3/45183 ,  H03F2203/45686

    Abstract: According to one general aspect, an apparatus may include a terminal configured to receive an analog input signal. In various embodiments, the apparatus may also include a multistage amplifier configured to amplify the analog input signal by an amount of gain. In some embodiments, the apparatus may include a distributed threshold adjuster interspersed between the stages of the multistage amplifier configured to adjust the DC voltage of the analog input signal to facilitate a decision by an analog-to-digital converter (ADC). In one embodiment, the apparatus may include the ADC configured to convert the amplified analog input signal to a digital output signal.

    Abstract translation: 根据一个一般方面，装置可以包括被配置为接收模拟输入信号的终端。 在各种实施例中，该装置还可以包括多级放大器，其被配置为将模拟输入信号放大一定量的增益。 在一些实施例中，该装置可以包括散布在多级放大器的级之间的分布式阈值调节器，其被配置为调整模拟输入信号的DC电压以便于模数转换器（ADC）的决定。 在一个实施例中，该装置可以包括被配置为将放大的模拟输入信号转换成数字输出信号的ADC。

    Threshold adjust system and method
    4.
    发明授权
    Threshold adjust system and method 失效
    阈值调整系统和方法

    公开(公告)号：US07769110B2

    公开(公告)日：2010-08-03

    申请号：US11128905

    申请日：2005-05-13

    Applicant: Afshin Momtaz

    Inventor： Afshin Momtaz

    IPC: H04L25/06

    CPC classification number: H04L25/061 ,  H04L7/033 ,  H04L25/03057

    Abstract: An adaptive algorithm is implemented that optimizes the slicer threshold by optimizing the tail distribution of a “+1” and “−1” histogram. Through the use of a low resolution and under-sampled ADC, a histogram of received bit may be created. The difference between the y-intersects of lines derived from the “+1” and “−1” histogram is used to determine an error function. The algorithm iteratively updates the threshold value based on this error function.

    Abstract translation: 实现了通过优化“+1”和“-1”直方图的尾部分布来优化限幅器阈值的自适应算法。 通过使用低分辨率和欠采样ADC，可以创建接收位的直方图。 使用从“+1”和“-1”直方图导出的线的y相交之间的差异来确定误差函数。 该算法基于该误差函数迭代地更新阈值。

    Decision feedback equalizer and clock and data recovery circuit for high speed applications
    5.
    发明授权
    Decision feedback equalizer and clock and data recovery circuit for high speed applications 有权
    决策反馈均衡器和时钟和数据恢复电路，适用于高速应用

    公开(公告)号：US07436882B2

    公开(公告)日：2008-10-14

    申请号：US10774965

    申请日：2004-02-09

    Applicant: Afshin Momtaz

    Inventor： Afshin Momtaz

    IPC: H03H7/30 ,  H03K5/159 ,  H03D3/24

    CPC classification number: H04L25/03057 ,  H04B10/2507 ,  H04L7/0004 ,  H04L7/033 ,  H04L2025/0349

    Abstract: A method for communicating data includes equalizing received data to reduce channel related distortion in the received data. A clock having frequency and/or phase fixed relative to the equalized data is extracted from the equalized data. The extracted clock is used to clock a retimer to generate recovered data.

    Abstract translation: 用于传送数据的方法包括均衡接收的数据以减少接收到的数据中的信道相关失真。 从均衡数据中提取相对于均衡数据具有频率和/或相位固定的时钟。 提取的时钟用于对重定时器进行计时以产生恢复的数据。

    Apparatus and method for analog-to-digital converter calibration
    7.
    发明申请
    Apparatus and method for analog-to-digital converter calibration 有权
    用于模数转换器校准的装置和方法

    公开(公告)号：US20080150772A1

    公开(公告)日：2008-06-26

    申请号：US12000757

    申请日：2007-12-17

    Applicant: Jun Cao ,  Afshin Momtaz

    Inventor： Jun Cao ,  Afshin Momtaz

    IPC: H03M1/10

    CPC classification number: H03M1/1061 ,  H03M1/362

    Abstract: Methods, systems, and apparatuses for calibration of analog to digital converters (ADC) are described herein. In an aspect, an ADC includes a plurality of slices. Each slice includes a digital to analog converter (DAC), a comparator, and a digital processing unit (DPU). The digital processing unit is electrically connected to the comparator and the DAC. In another aspect, an analog-to-digital converter includes an input module and an analog to digital converter core configured to receive an analog input from the input module and generate a digital output. The ADC is configured to adjust a precision of the analog to digital converter core based on a quality of the analog input signal.

    Abstract translation: 本文描述了用于模数转换器（ADC）的校准的方法，系统和装置。 在一方面，ADC包括多个切片。 每个片包括数模转换器（DAC），比较器和数字处理单元（DPU）。 数字处理单元电连接到比较器和DAC。 在另一方面，模数转换器包括被配置为从输入模块接收模拟输入并产生数字输出的输入模块和模数转换器内核。 ADC配置为基于模拟输入信号的质量来调整模数转换器内核的精度。

    Automatic gain control with three states of operation
    8.
    发明授权
    Automatic gain control with three states of operation 失效
    具有三种运行状态的自动增益控制

    公开(公告)号：US07385449B2

    公开(公告)日：2008-06-10

    申请号：US11729587

    申请日：2007-03-29

    Applicant: Namik Kemal Kocaman ,  Afshin Momtaz

    Inventor： Namik Kemal Kocaman ,  Afshin Momtaz

    IPC: H03G3/10

    CPC classification number: H03F3/45973 ,  H03F2200/435 ,  H03F2200/78 ,  H03G3/001 ,  H03G3/30

    Abstract: A method and apparatus for an automatic gain control circuit (AGC) that utilizes freezing and unfreezing states. A freezing process moves the AGC into a TRANSITION state from a NORMAL state, based on net change of VGA gain control codes over a monitoring time window. The freezing process then moves the AGC into a FROZEN state from the TRANSITION state, based on net change of VGA gain control codes over the monitoring time window. An unfreezing process moves the AGC into the NORMAL state from the FROZEN state, based on signal amplitude changes at the output of the VGA or other parameters of the VGA.

    Abstract translation: 一种利用冷冻和解​​冻状态的自动增益控制电路（AGC）的方法和装置。 基于监视时间窗口的VGA增益控制代码的净变化，冻结过程将AGC从NORMAL状态移动到TRANSITION状态。 基于监视时间窗口的VGA增益控制代码的净变化，冷冻过程然后将AGC从TRANSITION状态移动到FROZEN状态。 基于VGA输出端的VGA信号幅度变化或VGA的其他参数，解冻过程会将AGC从FROZEN状态移动到NORMAL状态。

    Digitally controlled threshold adjustment circuit
    10.
    发明授权
    Digitally controlled threshold adjustment circuit 有权
    数字控制阈值调节电路

    公开(公告)号：US07215171B2

    公开(公告)日：2007-05-08

    申请号：US11117767

    申请日：2005-04-28

    Applicant: Namik Kemal Kocaman ,  Afshin Momtaz

    Inventor： Namik Kemal Kocaman ,  Afshin Momtaz

    IPC: H03L5/00

    CPC classification number: H03K5/151 ,  H03K5/003 ,  H03K5/086

    Abstract: A threshold adjustment circuit including: a current DAC for supplying or sinking a varying current; a differential pair of thin oxide transistors coupled to the DAC and coupled together at a common source node; a power supply for providing a supply voltage having a voltage level above reliability of the thin oxide transistors; and a third transistor for maintaining voltage of the common source node above a predetermined level and to disable the threshold adjustment circuit. The bulk and source of each of the differential pair thin oxide transistors is coupled to the common source node and each of the differential pair thin oxide transistors is switched by a signal to keep each of the differential pair thin oxide transistors in saturation region.

    Abstract translation: 一种阈值调整电路，包括：用于提供或吸收变化电流的电流DAC; 耦合到DAC并在公共源节点处耦合在一起的薄氧化物晶体管的差分对; 用于提供具有高于薄氧化物晶体管的可靠性的电压电平的电源电压的电源; 以及第三晶体管，用于将公共源节点的电压维持在预定电平以上并禁止阈值调整电路。 每个差分对薄氧化物晶体管的体积和源极耦合到公共源节点，并且每个差分对薄氧化物晶体管被信号切换，以将每个差分对薄氧化物晶体管保持在饱和区域。

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