公开(公告)号：US20070285984A1

公开(公告)日：2007-12-13

申请号：US11766341

申请日：2007-06-21

申请人： Akira KATO ,  Toshihiro Tanaka ,  Takashi Yamaki

发明人： Akira KATO ,  Toshihiro Tanaka ,  Takashi Yamaki

IPC分类号： G11C11/41

CPC分类号： G11C16/0425

摘要： A data processing device which selects either emission of electrons from a nonvolatile memory cell or injection of electrons into it for each bit. A memory array includes a plurality of nonvolatile memory cells each having a pair of a first MOS transistor and a second MOS transistor where the first transistor has a charge retention layer and a memory gate and is used for data storage and the second transistor has a control gate and selectively connects the first transistor to a bit line. When negative voltage is applied to a memory gate, electrons held by a charge retention layer are emitted through hot carriers generated in a nonvolatile memory cell channel region for erasing; and when positive voltage is applied to the memory gate, electrons are injected into the charge retention layer through hot carriers generated in the nonvolatile memory cell channel region for writing and controls the generation and suppression of hot carriers by means of bit line voltage on each bit line.

摘要翻译： 一种数据处理装置，其选择来自非易失性存储单元的电子发射或向每一位注入电子。 存储器阵列包括多个非易失性存储单元，每个非易失性存储单元具有一对第一MOS晶体管和第二MOS晶体管，其中第一晶体管具有电荷保持层和存储栅极，并且用于数据存储，并且第二晶体管具有控制 并且选择性地将第一晶体管连接到位线。 当将负电压施加到存储器栅极时，由电荷保持层保持的电子通过在非易失性存储器单元通道区域中产生的热载流子发射以进行擦除; 并且当正电压施加到存储器栅极时，通过在非易失性存储器单元通道区域中产生的热载流子将电子注入电荷保持层中用于写入，并且通过每个位上的位线电压来控制热载流子的产生和抑制 线。

公开(公告)号：US07110295B2

公开(公告)日：2006-09-19

申请号：US11002802

申请日：2004-12-03

申请人： Jiro Ishikawa ,  Takashi Yamaki ,  Toshihiro Tanaka ,  Yukiko Umemoto ,  Akira Kato

发明人： Jiro Ishikawa ,  Takashi Yamaki ,  Toshihiro Tanaka ,  Yukiko Umemoto ,  Akira Kato

IPC分类号： G11C16/04

CPC分类号： G11C16/16 ,  G11C16/30

摘要： An erasing current is distributed to reduce a load of an internal power circuit and to decrease the number of drivers for erase. A semiconductor data processing device has: a memory array having nonvolatile memory cells arrayed in a matrix and divided into a plurality of erase blocks each instructed to be erased together; and a control circuit, wherein the control circuit controls both of two kinds of erasing voltages applied to the nonvolatile memory cell in the erase block instructed to be erased together to select an erase sector from the erase block for performing erase for each erase sector, thereby performing the erase for each erase sector in time division. Time division erase can distribute an erasing current. Two kinds of erasing voltages are used to select the erase sector. No specific drivers need be provided for each erase sector.

摘要翻译： 分配擦除电流以减少内部电源电路的负载并减少用于擦除的驱动器的数量。 一种半导体数据处理装置具有：存储阵列，其具有排列成矩阵状的非易失性存储单元，分为多个擦除块，分别被指示一起擦除; 以及控制电路，其中控制电路控制施加到擦除块中的非易失性存储单元的两种擦除电压，这些擦除块被一起擦除，以从擦除块中选择擦除扇区，以便为每个擦除扇区执行擦除，从而 按时间划分每个擦除扇区的擦除。 时分擦除可以分配擦除电流。 使用两种擦除电压来选择擦除扇区。 没有为每个擦除扇区提供特定的驱动程序。

公开(公告)号：US20050270851A1

公开(公告)日：2005-12-08

申请号：US11140741

申请日：2005-06-01

申请人： Akira Kato ,  Toshihiro Tanaka ,  Takashi Yamaki

发明人： Akira Kato ,  Toshihiro Tanaka ,  Takashi Yamaki

IPC分类号： G11C16/04 ,  G11C16/02 ,  G11C16/06 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/0425

摘要： A data processing device which selects either emission of electrons from a nonvolatile memory cell or injection of electrons into it for each bit. A memory array includes a plurality of nonvolatile memory cells each having a pair of a first MOS transistor and a second MOS transistor where the first transistor has a charge retention layer and a memory gate and is used for data storage and the second transistor has a control gate and selectively connects the first transistor to a bit line. When negative voltage is applied to a memory gate, electrons held by a charge retention layer are emitted through hot carriers generated in a nonvolatile memory cell channel region for erasing; and when positive voltage is applied to the memory gate, electrons are injected into the charge retention layer through hot carriers generated in the nonvolatile memory cell channel region for writing and controls the generation and suppression of hot carriers by means of bit line voltage on each bit line.

摘要翻译： 一种数据处理装置，其选择来自非易失性存储单元的电子发射或向每一位注入电子。 存储器阵列包括多个非易失性存储单元，每个非易失性存储单元具有一对第一MOS晶体管和第二MOS晶体管，其中第一晶体管具有电荷保持层和存储栅极，并且用于数据存储，并且第二晶体管具有控制 并且选择性地将第一晶体管连接到位线。 当将负电压施加到存储器栅极时，由电荷保持层保持的电子通过在非易失性存储器单元通道区域中产生的热载流子发射以进行擦除; 并且当正电压施加到存储器栅极时，通过在非易失性存储器单元通道区域中产生的热载流子将电子注入电荷保持层中用于写入，并且通过每个位上的位线电压来控制热载流子的产生和抑制 线。

公开(公告)号：US07551493B2

公开(公告)日：2009-06-23

申请号：US11766341

申请日：2007-06-21

申请人： Akira Kato ,  Toshihiro Tanaka ,  Takashi Yamaki

发明人： Akira Kato ,  Toshihiro Tanaka ,  Takashi Yamaki

IPC分类号： G11C11/30

CPC分类号： G11C16/0425

摘要： A data processing device which selects either emission of electrons from a nonvolatile memory cell or injection of electrons into it for each bit. A memory array includes a plurality of nonvolatile memory cells each having a pair of a first MOS transistor and a second MOS transistor where the first transistor has a charge retention layer and a memory gate and is used for data storage and the second transistor has a control gate and selectively connects the first transistor to a bit line. When negative voltage is applied to a memory gate, electrons held by a charge retention layer are emitted through hot carriers generated in a nonvolatile memory cell channel region for erasing; and when positive voltage is applied to the memory gate, electrons are injected into the charge retention layer through hot carriers generated in the nonvolatile memory cell channel region for writing and controls the generation and suppression of hot carriers by means of bit line voltage on each bit line.

摘要翻译： 一种数据处理装置，其选择来自非易失性存储单元的电子发射或向每一位注入电子。 存储器阵列包括多个非易失性存储单元，每个非易失性存储单元具有一对第一MOS晶体管和第二MOS晶体管，其中第一晶体管具有电荷保持层和存储栅极，并且用于数据存储，并且第二晶体管具有控制 并且选择性地将第一晶体管连接到位线。 当将负电压施加到存储器栅极时，由电荷保持层保持的电子通过在非易失性存储器单元通道区域中产生的热载流子发射以进行擦除; 并且当正电压施加到存储器栅极时，通过在非易失性存储器单元通道区域中产生的热载流子将电子注入电荷保持层中用于写入，并且通过每个位上的位线电压来控制热载流子的产生和抑制 线。

公开(公告)号：US07248504B2

公开(公告)日：2007-07-24

申请号：US11140741

申请日：2005-06-01

申请人： Akira Kato ,  Toshihiro Tanaka ,  Takashi Yamaki

发明人： Akira Kato ,  Toshihiro Tanaka ,  Takashi Yamaki

IPC分类号： G11C11/34

CPC分类号： G11C16/0425

摘要： A data processing device which selects either emission of electrons from a nonvolatile memory cell or injection of electrons into it for each bit. A memory array includes a plurality of nonvolatile memory cells each having a pair of a first MOS transistor and a second MOS transistor where the first transistor has a charge retention layer and a memory gate and is used for data storage and the second transistor has a control gate and selectively connects the first transistor to a bit line. When negative voltage is applied to a memory gate, electrons held by a charge retention layer are emitted through hot carriers generated in a nonvolatile memory cell channel region for erasing; and when positive voltage is applied to the memory gate, electrons are injected into the charge retention layer through hot carriers generated in the nonvolatile memory cell channel region for writing and controls the generation and suppression of hot carriers by means of bit line voltage on each bit line.

摘要翻译： 一种数据处理装置，其选择来自非易失性存储单元的电子发射或向每一位注入电子。 存储器阵列包括多个非易失性存储单元，每个非易失性存储单元具有一对第一MOS晶体管和第二MOS晶体管，其中第一晶体管具有电荷保持层和存储栅极，并且用于数据存储，并且第二晶体管具有控制 并且选择性地将第一晶体管连接到位线。 当将负电压施加到存储器栅极时，由电荷保持层保持的电子通过在非易失性存储器单元通道区域中产生的热载流子发射以进行擦除; 并且当正电压施加到存储器栅极时，通过在非易失性存储器单元通道区域中产生的热载流子将电子注入电荷保持层中用于写入，并且通过每个位上的位线电压来控制热载流子的产生和抑制 线。

公开(公告)号：US20050128815A1

公开(公告)日：2005-06-16

申请号：US11002802

申请日：2004-12-03

申请人： Jiro Ishikawa ,  Takashi Yamaki ,  Toshihiro Tanaka ,  Yukiko Umemoto ,  Akira Kato

发明人： Jiro Ishikawa ,  Takashi Yamaki ,  Toshihiro Tanaka ,  Yukiko Umemoto ,  Akira Kato

IPC分类号： G11C16/02 ,  G11C7/00 ,  G11C16/06 ,  G11C16/16 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/16 ,  G11C16/30

摘要： An erasing current is distributed to reduce a load of an internal power circuit and to decrease the number of drivers for erase. A semiconductor data processing device has: a memory array having nonvolatile memory cells arrayed in a matrix and divided into a plurality of erase blocks each instructed to be erased together; and a control circuit, wherein the control circuit controls both of two kinds of erasing voltages applied to the nonvolatile memory cell in the erase block instructed to be erased together to select an erase sector from the erase block for performing erase for each erase sector, thereby performing the erase for each erase sector in time division. Time division erase can distribute an erasing current. Two kinds of erasing voltages are used to select the erase sector. No specific drivers need be provided for each erase sector.

摘要翻译： 分配擦除电流以减少内部电源电路的负载并减少用于擦除的驱动器的数量。 一种半导体数据处理装置具有：存储阵列，其具有排列成矩阵状的非易失性存储单元，分为多个擦除块，分别被指示一起擦除; 以及控制电路，其中控制电路控制施加到擦除块中的非易失性存储单元的两种擦除电压，这些擦除块被一起擦除，以从擦除块中选择擦除扇区，以便为每个擦除扇区执行擦除，从而 按时间划分每个擦除扇区的擦除。 时分擦除可以分配擦除电流。 使用两种擦除电压来选择擦除扇区。 没有为每个擦除扇区提供特定的驱动程序。

公开(公告)号：US08017986B2

公开(公告)日：2011-09-13

申请号：US12718111

申请日：2010-03-05

申请人： Toshihiro Tanaka ,  Yukiko Umemoto ,  Mitsuru Hiraki ,  Yutaka Shinagawa ,  Masamichi Fujito ,  Kazufumi Suzukawa ,  Hiroyuki Tanikawa ,  Takashi Yamaki ,  Yoshiaki Kamigaki ,  Shinichi Minami ,  Kozo Katayama ,  Nozomu Matsuzaki

发明人： Toshihiro Tanaka ,  Yukiko Umemoto ,  Mitsuru Hiraki ,  Yutaka Shinagawa ,  Masamichi Fujito ,  Kazufumi Suzukawa ,  Hiroyuki Tanikawa ,  Takashi Yamaki ,  Yoshiaki Kamigaki ,  Shinichi Minami ,  Kozo Katayama ,  Nozomu Matsuzaki

IPC分类号： H01L29/788

CPC分类号： G11C16/26 ,  G11C5/025 ,  G11C8/08 ,  G11C16/04 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30 ,  H01L21/28 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/7885 ,  H01L29/792

摘要： A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc

摘要翻译： 半导体器件包括多个非易失性存储单元（1）。 每个非易失性存储单元包括用于信息存储的MOS型第一晶体管部分（3）和选择第一晶体管部分的MOS型第二晶体管部分（4）。 第二晶体管部分具有连接到位线的位线电极（16）和连接到控制栅极控制线的控制栅电极（18）。 第一晶体管部分具有连接到源极线的源极线电极（10），连接到存储器栅极控制线的存储栅电极（14）和直接位于存储栅电极下方的电荷存储区域（11）。 第二晶体管部分的栅极耐受电压低于第一晶体管部分的栅极耐受电压。 假设第二晶体管部分的栅极绝缘膜的厚度被定义为tc，并且第一晶体管部分的栅极绝缘膜的厚度被定义为tm，它们具有tc

公开(公告)号：US07414283B2

公开(公告)日：2008-08-19

申请号：US11415129

申请日：2006-05-02

申请人： Toshihiro Tanaka ,  Yukiko Umemoto ,  Mitsuru Hiraki ,  Yutaka Shinagawa ,  Masamichi Fujito ,  Kazufumi Suzukawa ,  Hiroyuki Tanikawa ,  Takashi Yamaki ,  Yoshiaki Kamigaki ,  Shinichi Minami ,  Kozo Katayama ,  Nozomu Matsuzaki

发明人： Toshihiro Tanaka ,  Yukiko Umemoto ,  Mitsuru Hiraki ,  Yutaka Shinagawa ,  Masamichi Fujito ,  Kazufumi Suzukawa ,  Hiroyuki Tanikawa ,  Takashi Yamaki ,  Yoshiaki Kamigaki ,  Shinichi Minami ,  Kozo Katayama ,  Nozomu Matsuzaki

IPC分类号： H01L29/788

CPC分类号： G11C16/26 ,  G11C5/025 ,  G11C8/08 ,  G11C16/04 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30 ,  H01L21/28 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/7885 ,  H01L29/792

摘要： A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc

摘要翻译： 半导体器件包括多个非易失性存储单元（1）。 每个非易失性存储单元包括用于信息存储的MOS型第一晶体管部分（3）和选择第一晶体管部分的MOS型第二晶体管部分（4）。 第二晶体管部分具有连接到位线的位线电极（16）和连接到控制栅极控制线的控制栅电极（18）。 第一晶体管部分具有连接到源极线的源极线电极（10），连接到存储器栅极控制线的存储栅电极（14）和直接位于存储栅电极下方的电荷存储区域（11）。 第二晶体管部分的栅极耐受电压低于第一晶体管部分的栅极耐受电压。 假设第二晶体管部分的栅极绝缘膜的厚度被定义为tc，并且第一晶体管部分的栅极绝缘膜的厚度被定义为tm，它们具有tc

公开(公告)号：US20060044871A1

公开(公告)日：2006-03-02

申请号：US11195684

申请日：2005-08-03

申请人： Hiroyuki Tanikawa ,  Toshihiro Tanaka ,  Yutaka Shinagawa ,  Takashi Yamaki

发明人： Hiroyuki Tanikawa ,  Toshihiro Tanaka ,  Yutaka Shinagawa ,  Takashi Yamaki

IPC分类号： G11C16/06

CPC分类号： G11C16/344

摘要： The present invention is directed to realize both higher reading speed and assurance of the larger number of rewriting times for a nonvolatile memory. A semiconductor integrated circuit has a first nonvolatile memory area and a second nonvolatile memory area for storing information in accordance with a threshold voltage which varies. One or plural conditions out of erase verify determination memory gate voltage, erase verify determination memory current, write verify determination memory gate voltage, write verify determination memory current, erase voltage, erase voltage application time, write voltage, and write voltage application time in the first nonvolatile memory area is/are made different from that/those in the second nonvolatile memory area, speed of reading information stored in the first nonvolatile memory area is higher than that of reading information stored in the second nonvolatile memory area, and the assured number of rewriting times in the second nonvolatile memory area is larger than that in the first nonvolatile memory area.

摘要翻译： 本发明旨在实现更高的读取速度和对非易失性存储器的更大数量的重写时间的保证。 半导体集成电路具有第一非易失性存储区域和用于根据变化的阈值电压存储信息的第二非易失性存储区域。 擦除验证存储器栅极电压，擦除验证确定存储器电流，写入验证确定存储器栅极电压，写入验证确定存储器电流，擦除电压，擦除电压施加时间，写入电压和写入电压施加时间中的一个或多个条件 第一非易失性存储器区域与第二非易失性存储区域中的那些不同，第一非易失性存储区域中存储的读取信息的速度高于存储在第二非易失性存储区域中的读取信息的速度，并且确定的数量 在第二非易失性存储器区域中的重写次数大于第一非易失性存储器区域中的重写时间。

公开(公告)号：US06963507B2

公开(公告)日：2005-11-08

申请号：US10419228

申请日：2003-04-21

申请人： Toshihiro Tanaka ,  Yutaka Shinagawa ,  Kazufumi Suzukawa ,  Masamichi Fujito ,  Takashi Yamaki ,  Kiichi Makuta ,  Masashi Wada ,  Yoshiki Kawajiri

发明人： Toshihiro Tanaka ,  Yutaka Shinagawa ,  Kazufumi Suzukawa ,  Masamichi Fujito ,  Takashi Yamaki ,  Kiichi Makuta ,  Masashi Wada ,  Yoshiki Kawajiri

IPC分类号： G11C16/02 ,  G11C8/02 ,  G11C16/12 ,  G11C16/04

CPC分类号： G11C16/3459 ,  G11C16/12 ,  G11C2216/14

摘要： Disclosed is a nonvolatile memory with a shortened total write time, capable of stably writing data by making a write current constant while reducing fluctuations in a voltage generated by a booster circuit. In a nonvolatile memory such as a flash memory, data is determined at the time of writing operation. While skipping a bit corresponding to write data having the logic “1” (or logic “0”), writing operation to bits corresponding to write data having the logic “0” (or logic “1) is successively performed.