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    Logic circuitry-implemented bus buffer
    1.
    发明授权
    Logic circuitry-implemented bus buffer 有权
    逻辑电路实现的总线缓冲器

    公开(公告)号：US06714051B2

    公开(公告)日：2004-03-30

    申请号：US10309254

    申请日：2002-12-04

    申请人： Akira Takiba ,  Masanori Kinugasa ,  Takumi Tsukazaki ,  Toru Fujii ,  Masaru Mizuta

    发明人： Akira Takiba ,  Masanori Kinugasa ,  Takumi Tsukazaki ,  Toru Fujii ,  Masaru Mizuta

    IPC分类号： H03K190175

    CPC分类号： G06F13/4027 ,  Y02D10/14 ,  Y02D10/151

    摘要： A bus buffer has a controller to generate several control signals; a first terminal via which a first-directional signal is input whereas a second-directional signal is output; a second terminal via which the first-directional signal is output whereas the second-directional signal is input; a first-directional signal processor, provided between the first and second terminals, having a first internal circuit and a first output buffer; a second-directional signal processor, provided between the second and first terminals, having a second internal circuit and a second output buffer; a first input buffer having a first input holder to disactivate the first internal circuit and the first output buffer by using at least one of the control signals; and a second input buffer having a second input holder to disactivate the second internal circuit and the second output buffer by using the at least one control signal, for holding the input to the input buffers at a certain level to decrease a current to pass these circuits, thus achieving low power consumption.

    摘要翻译： 总线缓冲器具有控制器以产生若干控制信号; 输入第一方向信号的第一终端，输出第二方向信号; 输出第一方向信号的第二端子，而输入第二方向信号; 设置在第一和第二终端之间的具有第一内部电路和第一输出缓冲器的第一方向信号处理器; 设置在第二和第一终端之间的具有第二内部电路和第二输出缓冲器的第二方向信号处理器; 第一输入缓冲器，具有通过使用至少一个控制信号来去激活第一内部电路和第一输出缓冲器的第一输入保持器; 以及具有第二输入保持器的第二输入缓冲器，用于通过使用所述至少一个控制信号去激活第二内部电路和第二输出缓冲器，以将输入保持在一定电平的输入缓冲器以减小电流以通过这些电路 ，从而实现低功耗。

    Protection circuit provided in semiconductor circuit
    2.
    发明授权
    Protection circuit provided in semiconductor circuit 失效
    半导体电路中提供的保护电路

    公开(公告)号：US06762460B2

    公开(公告)日：2004-07-13

    申请号：US09983124

    申请日：2001-10-23

    申请人： Akira Takiba ,  Masanori Kinugasa ,  Yoshimitsu Itoh ,  Masaru Mizuta

    发明人： Akira Takiba ,  Masanori Kinugasa ,  Yoshimitsu Itoh ,  Masaru Mizuta

    IPC分类号： H01L2362

    CPC分类号： H01L27/0266

    摘要： A protection circuit including a power supply terminal supplied with a power supply potential, a reference terminal supplied with a reference potential, and a first p-channel MOS transistor having a first gate, a first source, a first drain and a first back gate. The first gate, the first source and the first back gate are connected to the power supply terminal. Also included is a second p-channel MOS transistor having a second gate, a second source, a second drain and the first back gate, in which the second source of the second p-channel MOS transistor is connected to the first drain of the first p-channel MOS transistor, and the second gate and the second drain of the second p-channel MOS transistor is connected to the reference terminal. The circuit also includes a first n-channel MOS transistor having a third gate, a third source, a third drain and a second back gate, in which the third gate, in which the third source and the second back gate of the first n-channel MOS transistor are connected to the reference terminal, and including a second n-channel MOS transistor having a fourth gate, a fourth source, a fourth drain and the second back gate, in which the fourth source of the second n-channel MOS transistor are connected to the third drain of the first n-channel MOS transistor, and the fourth gate and the fourth drain of the second n-channel MOS transistor are connected to the power supply terminal.

    摘要翻译： 一种保护电路，包括供电电源的电源端子，提供有参考电位的基准端子以及具有第一栅极，第一源极，第一漏极和第一后栅极的第一p沟道MOS晶体管。 第一栅极，第一源极和第一后栅极连接到电源端子。 还包括具有第二栅极，第二源极，第二漏极和第一后栅极的第二p沟道MOS晶体管，其中第二P沟道MOS晶体管的第二源极连接到第一栅极 p沟道MOS晶体管，第二p沟道MOS晶体管的第二栅极和第二漏极连接到参考端子。 该电路还包括具有第三栅极，第三源极，第三漏极和第二后栅极的第一n沟道MOS晶体管，其中第三栅极，其中第一栅极，第三漏极和第二栅极的第三源极和第二反向栅极， 沟道MOS晶体管连接到参考端，并且包括具有第四栅极，第四源极，第四漏极和第二后栅极的第二n沟道MOS晶体管，其中第二n沟道MOS晶体管的第四源极 连接到第一n沟道MOS晶体管的第三漏极，第二n沟道MOS晶体管的第四栅极和第四漏极连接到电源端子。

    Temperature detector circuit having function for restricting occurrence of output error caused by dispersion in element manufacture
    3.
    发明授权
    Temperature detector circuit having function for restricting occurrence of output error caused by dispersion in element manufacture 失效
    温度检测电路具有限制元件制造中色散引起的输出误差的发生的功能

    公开(公告)号：US06337603B1

    公开(公告)日：2002-01-08

    申请号：US09606016

    申请日：2000-06-29

    申请人： Masanori Kinugasa ,  Yoshimitsu Itoh ,  Masaru Mizuta ,  Akira Takiba ,  Shinji Inada

    发明人： Masanori Kinugasa ,  Yoshimitsu Itoh ,  Masaru Mizuta ,  Akira Takiba ,  Shinji Inada

    IPC分类号： H03B504

    CPC分类号： H03B5/04 ,  H03B5/36

    摘要： A temperature detector circuit for converting a forward drop voltage of a diode to digital data by means of an AD converter is provided. In order to restrict an occurrence of an output error caused by dispersion in diode manufacture, correction data according to digital data obtained by the AD converter is stored in advance in a storage circuit under a known arbitrary temperature condition, and subtraction is performed between digital data obtained by the AD converter under an unknown temperature condition and correction data read from a storage circuit, thereby to perform correction.

    摘要翻译： 提供一种用于通过AD转换器将二极管的正向压降电压转换为数字数据的温度检测器电路。 为了限制二极管制造中由色散引起的输出误差的发生，根据AD转换器获得的数字数据的校正数据预先存储在已知的任意温度条件下的存储电路中，并且在数字数据 在未知温度条件下由AD转换器获得的校正数据和从存储电路读取的校正数据，从而进行校正。

    Oscillation circuit
    6.
    发明申请
    Oscillation circuit 审中-公开
    振荡电路

    公开(公告)号：US20070001771A1

    公开(公告)日：2007-01-04

    申请号：US11476554

    申请日：2006-06-29

    申请人： Chikahiro Hori ,  Akira Takiba ,  Masanori Kinugasa

    发明人： Chikahiro Hori ,  Akira Takiba ,  Masanori Kinugasa

    IPC分类号： H03K3/03

    CPC分类号： H03K3/0315 ,  H03K5/00006 ,  H03K5/133

    摘要： An oscillation circuit comprises a ring oscillator configured to have at least an odd number of stages of inverters, and a frequency multiplier section configured to output as a multiplied output, an exclusive OR of signals taken out from the inverters at least at two stages of the ring oscillator.

    摘要翻译： 振荡电路包括：环形振荡器，被配置为具有至少奇数级的反相器;以及倍增器部分，被配置为输出作为相乘的输出，至少在所述反相器的两个阶段从所述反相器中取出的信号的异或 环形振荡器。

    Switch circuit
    7.
    发明授权
    Switch circuit 失效
    开关电路

    公开(公告)号：US06924694B2

    公开(公告)日：2005-08-02

    申请号：US10647290

    申请日：2003-08-26

    申请人： Masanori Kinugasa ,  Akira Takiba

    发明人： Masanori Kinugasa ,  Akira Takiba

    IPC分类号： H01L21/822 ,  H01L27/04 ,  H03K17/60 ,  H03K17/687 ,  H03K19/0175 ,  H01L25/10

    CPC分类号： H03K17/6872 ,  H03K2217/0018

    摘要： A switch circuit formed on a semiconductor substrate, comprising: a first terminal to which a signal of transmission object is inputted; a second terminal from which a signal of transmission object is outputted; a first transistor formed in a first semiconductor region in said semiconductor substrate, which has one of a source and a drain terminals connected to said first terminal and another thereof connected to said second terminal; a control circuit which controls a gate voltage of said first transistor; and a first rectifying element which has an anode terminal connected to said first terminal, a cathode terminal connected to a power supply terminal of said control circuit, said first rectifying element being formed in a second semiconductor region in said semiconductor substrate separate from said first semiconductor region.

    摘要翻译： 一种形成在半导体衬底上的开关电路，包括：输入发送对象的信号的第一端子; 输出发送对象的信号的第二终端; 形成在所述半导体衬底中的第一半导体区域中的第一晶体管，其具有连接到所述第一端子的源极和漏极端子中的一个，并且另一个连接到所述第二端子; 控制所述第一晶体管的栅极电压的控制电路; 以及第一整流元件，其具有连接到所述第一端子的阳极端子，连接到所述控制电路的电源端子的阴极端子，所述第一整流元件形成在所述半导体衬底中的与所述第一半导体分离的第二半导体区域中 地区。

    Auto-clear circuit and integrated circuit including an auto-clear circuit for initialization based on a power supply voltage
    8.
    发明授权
    Auto-clear circuit and integrated circuit including an auto-clear circuit for initialization based on a power supply voltage 失效
    自动清除电路和集成电路，包括基于电源电压进行初始化的自动清除电路

    公开(公告)号：US5825220A

    公开(公告)日：1998-10-20

    申请号：US778743

    申请日：1997-01-02

    申请人： Masanori Kinugasa ,  Hiroshi Shigehara ,  Akira Takiba

    发明人： Masanori Kinugasa ,  Hiroshi Shigehara ,  Akira Takiba

    IPC分类号： H03K3/356 ,  H03K17/22

    CPC分类号： H03K3/356008 ,  H03K17/223

    摘要： An auto-clear circuit which has a switch device connected between a power supply voltage terminal and first and second nodes, and a potential division device, connected between the first node and a ground terminal, for outputting a first potential obtained by dividing a potential of the first node. Also included is a charge/discharge device, connected between the second node and a ground terminal, for charging or discharging the second node on the basis of the first potential output from the potential division device, and a latch device for holding a potential of the second node to output a signal from an output terminal, and supplying the signal to the switch device to control an opening/closing operation.

    摘要翻译： 一种自动清除电路，其具有连接在电源电压端子和第一和第二节点之间的开关装置，以及连接在第一节点和接地端子之间的电位分配装置，用于输出通过将第一电位除以 第一个节点。 还包括连接在第二节点和接地端子之间的充电/放电装置，用于基于来自电势分配装置的第一电位输出对第二节点进行充电或放电;以及锁存装置，用于保持电位 第二节点输出来自输出端子的信号，并将信号提供给开关装置以控制开/关操作。

    BUS SWITCH WITH LEVEL SHIFTING
    9.
    发明申请
    BUS SWITCH WITH LEVEL SHIFTING 失效
    总线开关水平移位

    公开(公告)号：US20080028121A1

    公开(公告)日：2008-01-31

    申请号：US11778275

    申请日：2007-07-16

    申请人： Akira Takiba ,  Masaru Mizuta

    发明人： Akira Takiba ,  Masaru Mizuta

    IPC分类号： G06F13/36

    CPC分类号： G06F13/4072

    摘要： A bus switch with level shifting may include a first terminal configured to receive and output a first power supply voltage higher than a reference voltage, a second terminal configured to receive and output a second power supply voltage higher than the first power supply voltage, an output control terminal to which a control signal for controlling a switching between an output permitted state and an output prohibited state is inputted, a first switching element provided between the first terminal and the second terminal and having a gate, a gate control circuit to which signals are inputted from the output control terminal and the second terminal, which supplies gate voltage to the gate of the first switching element, and which controls the first switching element to be conducting or to be non-conducting, and a second switching device provided between a power source of the second power supply voltage and the second terminal, and configured to switch between conducting and non-conducting in accordance with the electric potential of the second terminal

    摘要翻译： 具有电平移位的总线开关可以包括被配置为接收和输出高于参考电压的第一电源电压的第一端子，被配置为接收和输出高于第一电源电压的第二电源电压的第二端子， 输入用于控制输出允许状态和输出禁止状态之间的切换的控制信号的控制端子，设置在第一端子和第二端子之间并具有栅极的第一开关元件，栅极控制电路，信号为 从输出控制端子和第二端子输入，该第二端子将栅极电压提供给第一开关元件的栅极，并且控制第一开关元件导通或不导通;以及第二开关器件，其设置在功率 第二电源电压源和第二端子，并被配置为在导通和非导通之间切换 根据第二终端的电位

    Semiconductor device
    10.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US6054736A

    公开(公告)日：2000-04-25

    申请号：US076874

    申请日：1998-05-13

    申请人： Hiroshi Shigehara ,  Masanori Kinugasa ,  Akira Takiba ,  Ryouichi Isohata

    发明人： Hiroshi Shigehara ,  Masanori Kinugasa ,  Akira Takiba ,  Ryouichi Isohata

    IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/68 ,  H01L21/265

    CPC分类号： H01L29/66659 ,  H01L29/7835

    摘要： A semiconductor device of the present invention comprises: a semiconductor substrate of a first conductive type; a gate electrode formed on the semiconductor substrate; a first semiconductor region of a second conductive type different from the first conductive type, the first semiconductor region being formed on the semiconductor substrate in one of both side regions of the gate electrode so as to be adjacent to the gate electrode; a second semiconductor region of the second conductive type formed on the semiconductor substrate in the other region of the both side regions of the gate electrode so as to be adjacent to the gate electrode; a third semiconductor region of the second conductive type formed in the one region so as to be isolated from the first semiconductor region and to be spaced from the second semiconductor region by a greater distance than that between the first and third semiconductor regions; a connecting portion for connecting the first semiconductor region to the third semiconductor region, the connecting portion having a higher resistance than those of the first and third semiconductor regions; a first electrode formed so as to be electrically connected to the third semiconductor region; and a second electrode formed so as to be electrically connected to the second semiconductor region. Thus, it is possible to prevent the element characteristics from deteriorating even if a surge voltage is applied and to decrease the element size.

    摘要翻译： 本发明的半导体器件包括：第一导电类型的半导体衬底; 形成在所述半导体衬底上的栅电极; 与所述第一导电类型不同的第二导电类型的第一半导体区域，所述第一半导体区域形成在所述栅电极的两个侧面区域之一的所述半导体衬底上，以与所述栅电极相邻; 第二导电类型的第二半导体区域形成在栅电极的两侧区域的另一区域中的半导体衬底上，以便与栅电极相邻; 所述第二导电类型的第三半导体区域形成在所述一个区域中，以与所述第一半导体区域隔离并且与所述第二半导体区域间隔开比距所述第一和第三半导体区域之间更大的距离; 连接部分，用于将第一半导体区域连接到第三半导体区域，连接部分具有比第一和第三半导体区域更高的电阻; 形成为与第三半导体区域电连接的第一电极; 以及形成为与第二半导体区域电连接的第二电极。 因此，即使施加浪涌电压也可以防止元件特性劣化并且减小元件尺寸。