公开(公告)号：US06343081B1

公开(公告)日：2002-01-29

申请号：US09121992

申请日：1998-07-24

申请人： Alain Blanc ,  Bernard Brezzo ,  Pierre Debord ,  Patrick Jeanniot ,  Alain Saurel

发明人： Alain Blanc ,  Bernard Brezzo ,  Pierre Debord ,  Patrick Jeanniot ,  Alain Saurel

IPC分类号： H04L1256

CPC分类号： H04L49/3081 ,  H04L12/5601 ,  H04L49/1507 ,  H04L49/1553 ,  H04L49/201 ,  H04L49/25 ,  H04L49/506 ,  H04L2012/5679

摘要： A method and apparatus for managing contention in a self-routing switching architecture based on a set of n×n individual switching structures that are connected in a port expansion mode by means of fan-out and fan-in circuits providing access of the Switch Core Access Layer (SCAL) to the different input and output ports of the switching core. The fan-in circuits use an arbitration mechanism for providing a token to the switch that is allowed to deliver the next cell and the arbiter operates from a detection of a special comma character in accordance with the 8B/10B coding scheme which is introduced in the data flow between the individual switching structures and the fan-in circuits. This provides a compensation for the difference in transfer delays of the cells even when high switching speed and long length of the physical media are involved.

摘要翻译： 一种用于管理自路由交换架构中的争用的方法和装置，所述方法和装置基于通过扇出方式连接的端口扩展模式的一组nxn个别交换结构，以及提供交换机核心接入层 （SCAL）到交换核心的不同输入和输出端口。 扇入电路使用仲裁机制，用于向交换机提供令牌，该令牌被允许传送下一个小区，并且仲裁器根据在8B中引入的8B / 10B编码方案的特殊逗号字符的检测来操作 各个开关结构和扇入电路之间的数据流。 即使涉及物理介质的高切换速度和长的长度，这也为单元的传送延迟的差异提供了补偿。

公开(公告)号：US06606300B1

公开(公告)日：2003-08-12

申请号：US09219081

申请日：1998-12-22

申请人： Alain Blanc ,  Pierre Debord ,  Alain Saurel ,  Bernard Brezzo

发明人： Alain Blanc ,  Pierre Debord ,  Alain Saurel ,  Bernard Brezzo

IPC分类号： H04L1256

CPC分类号： H04L49/3081 ,  H04L49/1507 ,  H04L49/201 ,  H04L49/25 ,  H04L49/50 ,  H04L49/506 ,  H04L2012/563 ,  H04L2012/5672 ,  H04Q11/0478

摘要： A flow control process for a switching system having at least one switch core connected through serial communication links to remote and distributed Protocol Adapters or Protocol Engines through Switch Core Access Layer (SCAL) elements. For each input port i, the SCAL element contains a receive Protocol Interface corresponding to the adapter assigned to the input port i and a first serializer for providing attachment to the switch core by means of a first serial communication link. When the cells are received in the switch core, they are deserialized by means of a first deserializer. At each output port, the cells are serialized again by means of a second serializer and then transmitted via a second serial communication link, to the appropriate SCAL. The SCAL contains a second deserializer and a transmit Protocol Interface circuit for permitting attachment of the Protocol Adapter. The flow control process permits two flow control signals, a flow control receive (FCR) from the core to the SCAL, and a flow control transmit (FCX) from the SCAL back to the core. For transmission of the FCR signal in response to the detection of local saturation in the switch core, the process causes transfer of an internal FCR signal to the serializer located within the saturated core. The FCR is introduced in the normal data flow to be conveyed through the second serial link to the remote SCAL corresponding to the saturated input port of the core. An internal control signal can be transmitted to the Protocol Interface that is originating too many cells which results in the overloaded input port of the core. For the transmission of the FCX signal in response to the detection of a saturated Protocol Interface element at one output port, the process generates an internal control signal to the serializer located in the SCAL element. The serializer can introduce a FCX signal in the normal data flow which is conveyed to the core and then decoded by the deserializer in the core. Thus, the core can be informed of the saturation condition that has occurred in the considered output port. Particular adaptations are provided in which the switching system is arranged in a set of individual switching structures mounted in a port expansion mode.

公开(公告)号：US06597656B1

公开(公告)日：2003-07-22

申请号：US09317006

申请日：1999-05-24

申请人： Alain Blanc ,  Sylvie Gohl ,  Alain Saurel ,  Bernard Brezzo ,  Jean-Claude Robbe

发明人： Alain Blanc ,  Sylvie Gohl ,  Alain Saurel ,  Bernard Brezzo ,  Jean-Claude Robbe

IPC分类号： H04L122

CPC分类号： H04L12/5601 ,  H04L49/108 ,  H04L49/309 ,  H04L49/455 ,  H04L2012/5627 ,  H04L2012/5647

摘要： A switching system having at least two switch fabrics. Each fabric has a switch core and a set of SCAL (Switch Core Access Layer) receive and transmit elements. The switch cores are preferably located in the same physical area but the SCALs may be distributed in different physical areas. Port Adapters distributed at different physical areas are connected to the switch fabrics via a particular SCAL element so that each switch core can receive cells from any port adapter and conversely any port adapter may receive data from either switch core. Control logic assigns a particular switch core to one port adapter for normal operations while reserving the other switch core for use when the first core is out of service. Each switch core has a mask mechanism which uses the value in a mask register to alter a bitmap value which controls the routing process. The mask registers in the two switch cores are loaded with complementary values.

摘要翻译： 一种具有至少两个交换结构的交换系统。 每个结构具有交换机核心和一组SCAL（交换机核心接入层）接收和发送元素。 交换机核心优选地位于相同的物理区域中，但是SCAL可以分布在不同的物理区域中。 分布在不同物理区域的端口适配器通过特定的SCAL元件连接到交换结构，使得每个交换机核心可以从任何端口适配器接收单元，相反，任何端口适配器可以从交换机核心接收数据。 控制逻辑将特定的交换机核心分配给一个端口适配器进行正常操作，同时在第一个核心停止工作时保留另一个交换机内核以供使用。 每个交换机核心都有一个掩码机制，使用掩码寄存器中的值来更改控制路由进程的位图值。 两个交换机核心中的掩码寄存器加载互补值。

公开(公告)号：US6108334A

公开(公告)日：2000-08-22

申请号：US992871

申请日：1997-12-17

申请人： Alain Blanc ,  Bernard Brezzo ,  Michel Poret ,  Alain Saurel

发明人： Alain Blanc ,  Bernard Brezzo ,  Michel Poret ,  Alain Saurel

IPC分类号： H04L12/70 ,  H04L12/933 ,  H04L12/935 ,  H04Q11/04 ,  H04L12/56

CPC分类号： H04L49/3081 ,  H04L49/1553 ,  H04Q11/0478 ,  H04L2012/5642

摘要： A switching system comprising a switching structure for routing cells from a set of M input ports towards a set of M output ports. The system includes a set of distributed individual Switch Core Access layer elements which communicate with one input and output port of the switching structure by means of a set of serial communication links. Each SCAL element provides attachment to at least one Protocol Adapter and comprises a set of circuits. The receive part of each circuit, which includes at least one first FIFO storage for storing the cells being received, receives the data cells from the attached Protocol Adapter and introduces at least one extra byte to every cell. Each transmit part of the destination circuit, which includes at least one second FIFO storage having a greater capacity than the first FIFO storage, receives all the cells that are generated at the corresponding output port and uses the at least one extra byte for cell buffering. Additionally, each distrubuted SCAL element comprises control means for performing Time Division Multiplexing access of the FIFOs.

摘要翻译： 一种交换系统，包括用于将一组M个输入端口的单元路由到一组M个输出端口的交换结构。 该系统包括一组分布式的交换机核心接入层元件，它们通过一组串行通信链路与交换结构的一个输入和输出端口通信。 每个SCAL元件提供至少一个协议适配器的附件，并且包括一组电路。 每个电路的接收部分包括至少一个用于存储接收的单元的第一FIFO存储器，从附加的协议适配器接收数据单元，并向每个单元引入至少一个额外的字节。 目的地电路的每个发送部分包括具有比第一FIFO存储器更大的容量的至少一个第二FIFO存储器，接收在相应输出端口处生成的所有单元，并使用该至少一个额外字节用于单元缓冲。 另外，每个分散的SCAL元件包括用于执行FIFO的时分多路复用访问的控制装置。

公开(公告)号：US06570845B1

公开(公告)日：2003-05-27

申请号：US09317322

申请日：1999-05-24

申请人： Alain Blanc ,  Bernard Brezzo ,  Alain Saurel

发明人： Alain Blanc ,  Bernard Brezzo ,  Alain Saurel

IPC分类号： G06F1100

CPC分类号： H04L12/5601 ,  H04L49/108 ,  H04L49/153 ,  H04L49/256 ,  H04L49/309 ,  H04L2012/5627 ,  H04L2012/5681

摘要： A switching system receives a data cell from a set of n input ports for routing to one or more output ports in accordance with the contents of a bitmap value retrieved from the cell upon its receipt. The system has a module comprising a shared buffer for storing the cells which are to be routed and a mask mechanism with a mask register for altering the value of the bitmap before it is used for controlling the routing process. As a result of operation of the mask mechanism, a cell is either transported to an output port or discarded. Two switching systems are combined in first and second switch fabrics, each having a switch core and a set of switch core access layer (SCAL) elements. Each SCAL element respectively comprises a SCAL Receive element and a SCAL Xmit element for permitting access to input and output ports of one of the switching systems.

摘要翻译： 交换系统根据从单元接收到的位图值的内容，从一组n个输入端口接收用于路由到一个或多个输出端口的数据单元。 该系统具有模块，该模块包括用于存储待路由的单元的共享缓冲器和具有用于在用于控制路由过程之前改变位图的值的掩码寄存器的掩码机制。 作为掩模机构的操作的结果，单元被传送到输出端口或被丢弃。 两个交换系统组合在第一和第二交换机结构中，每个具有交换机核心和一组交换机核心接入层（SCAL）元件。 每个SCAL元件分别包括SCAL接收元件和SCAL Xmit元件，用于允许访问一个交换系统的输入和输出端口。

公开(公告)号：US06452900B1

公开(公告)日：2002-09-17

申请号：US09207061

申请日：1998-12-07

申请人： Alain Blanc ,  Bernard Brezzo ,  Pierre Debord ,  Albert Widmer

发明人： Alain Blanc ,  Bernard Brezzo ,  Pierre Debord ,  Albert Widmer

IPC分类号： H04L100

CPC分类号： H04L47/263 ,  H04L12/5602 ,  H04L47/10 ,  H04L49/255 ,  H04L49/3081 ,  H04L49/45 ,  H04L49/506 ,  H04L2012/5615 ,  H04L2012/563 ,  H04L2012/5635

摘要： A flow control process for a switching architecture having a central switch core with associated distributed Switch Core Access Layers communicating with the core by means of serial data communication links. The serial links carry data flows that are coded in accordance with the 8B/10B coding, where two among the three comma characters are used for creating an additional specialized flow control channel. When the cells are idle or empty, the nature of the comma character that appears at the beginning of the cell provides the appropriate flow control bit information. For instance, should the K.28.5 character be detected, the receiving entity (either the switching structure or a distributed SCAL element) decodes the character as positive flow control information, corresponding to a request to reduce the incoming data flow. Also, should the K.28.1 character be decoded, then the receiving entity decodes this as information according to which no reduction in the data flow is requested. When the incoming flow provides data cells, the invention uses a predetermined bit within the data cell, generally that immediately following the beginning of the cell, in order to carry the flow control information.

摘要翻译： 一种用于具有中央交换机核心的交换架构的流控制过程，其具有通过串行数据通信链路与核心通信的相关联的分布式交换机核心接入层。 串行链路携带根据8B / 10B编码编码的数据流，其中三个逗号中的两个用于创建附加的专用流控制信道。 当单元格空闲或空闲时，出现在单元开头的逗号字符的性质提供了适当的流控制位信息。 例如，如果检测到K.28.5字符，接收实体（交换结构或分布式SCAL元素）将该字符解码为正流量控制信息，对应于减少传入数据流的请求。 此外，如果解码了K.28.1字符，则接收实体将其解码为信息，根据该信息不要求数据流的减少。 当传入流提供数据单元时，本发明使用数据单元内的预定位，通常是在单元开始之后，为了承载流量控制信息。

公开(公告)号：US07061909B2

公开(公告)日：2006-06-13

申请号：US09950897

申请日：2001-09-10

申请人： Alain Blanc ,  Bernard Brezzo ,  Rene Gallezot ,  Franco Le Maut ,  Thierry Roman ,  Daniel Wind

发明人： Alain Blanc ,  Bernard Brezzo ,  Rene Gallezot ,  Franco Le Maut ,  Thierry Roman ,  Daniel Wind

IPC分类号： H04L12/56

CPC分类号： H04L49/201 ,  H04L49/103 ,  H04L49/3009 ,  H04L49/3018 ,  H04L49/3027

摘要： A data switch is provided which routes fixed-size data packets from input ports to output ports, using shared memory which holds a copy of each packet in buffers. Output ports have a queue which contains pointers to buffers holding packets bound for that port. The number of shared memory buffers holding packets is compared to the number of buffer pointers in the output queues. In this way, a Multicast Index (MCI), a metric of the level of multicast traffic, is derived. The switch includes a Switch Core Adaptation Layer (SCAL) which has a multicast input queue. Because traffic is handled based on priority class P, a multicast threshold MCT(P), associated with the multicast input queue, is established per priority. While receiving traffic, the MCI is updated and, for each priority class in each SCAL, the MCI is compared to the MCT(P) to determine whether corresponding multicast traffic must be held.

公开(公告)号：US20060025945A1

公开(公告)日：2006-02-02

申请号：US11235856

申请日：2005-09-27

申请人： Alain Blanc ,  Patrick Jeanniot

发明人： Alain Blanc ,  Patrick Jeanniot

IPC分类号： G06F19/00

CPC分类号： H04L25/03343 ,  H04L1/0001 ,  H04L1/20 ,  H04L7/0337 ,  H04L2025/03375

摘要： A method and systems for automatically adjusting the parameters of signal emitter in a synchronous high-speed transmission system, is disclosed. According to the method of the invention, the quality of a high-speed received signal is analyzed for a plurality of sets of parameter values and the one producing the best signal quality is selected. In a first embodiment, the quality of the high-speed received signal is determined by analyzing a digital eye characterizing the signal behavior, obtained by over-sampling the high-speed received signal. In a second embodiment, the quality of the high-speed received signal is determined by analyzing the behavior of the phase rotator used for data sampling. Finally, in a third embodiment, the quality of the high-speed received signal is determined by analyzing a digital eye, obtained by moving the position of a phase rotator from one end to the other and sampling data at each position.

摘要翻译： 公开了一种在同步高速传输系统中自动调整信号发射器参数的方法和系统。 根据本发明的方法，对多组参数值分析高速接收信号的质量，并选择产生最佳信号质量的参数值。 在第一实施例中，通过分析表征由高速接收信号过采样得到的信号行为的数字眼来确定高速接收信号的质量。 在第二实施例中，通过分析用于数据采样的相位旋转器的行为来确定高速接收信号的质量。 最后，在第三实施例中，通过分析通过将相位旋转器的位置从一端移动到另一端而获得的数字眼，并且在每个位置处采样数据来确定高速接收信号的质量。

公开(公告)号：US06990418B2

公开(公告)日：2006-01-24

申请号：US10697832

申请日：2003-10-30

申请人： Alain Blanc ,  Patrick Jeanniot

发明人： Alain Blanc ,  Patrick Jeanniot

IPC分类号： G01R13/00 ,  H04B17/00

CPC分类号： H04L25/03343 ,  H04L1/0001 ,  H04L1/20 ,  H04L7/0337 ,  H04L2025/03375

摘要： A method and systems for automatically adjusting the parameters of signal emitter in a synchronous high-speed transmission system, is disclosed. According to the method of the invention, the quality of a high-speed received signal is analyzed for a plurality of sets of parameter values and the one producing the best signal quality is selected. In a first embodiment, the quality of the high-speed received signal is determined by analyzing a digital eye characterizing the signal behavior, obtained by over-sampling the high-speed received signal. In a second embodiment, the quality of the high-speed received signal is determined by analyzing the behavior of the phase rotator used for data sampling. Finally, in a third embodiment, the quality of the high-speed received signal is determined by analyzing a digital eye, obtained by moving the position of a phase rotator from one end to the other and sampling data at each position.

公开(公告)号：US20070271050A1

公开(公告)日：2007-11-22

申请号：US11764453

申请日：2007-06-18

申请人： Alain Blanc ,  Patrick Jeanniot

发明人： Alain Blanc ,  Patrick Jeanniot

IPC分类号： G06F19/00

CPC分类号： H04L25/03343 ,  H04L1/0001 ,  H04L1/20 ,  H04L7/0337 ,  H04L2025/03375

摘要： A method and systems for automatically adjusting the parameters of signal emitter in a synchronous high-speed transmission system, is disclosed. According to the method of the invention, the quality of a high-speed received signal is analyzed for a plurality of sets of parameter values and the one producing the best signal quality is selected. In a first embodiment, the quality of the high-speed received signal is determined by analyzing a digital eye characterizing the signal behavior, obtained by over-sampling the high-speed received signal. In a second embodiment, the quality of the high-speed received signal is determined by analyzing the behavior of the phase rotator used for data sampling. Finally, in a third embodiment, the quality of the high-speed received signal is determined by analyzing a digital eye, obtained by moving the position of a phase rotator from one end to the other and sampling data at each position.

摘要翻译： 公开了一种在同步高速传输系统中自动调整信号发射器参数的方法和系统。 根据本发明的方法，对多组参数值分析高速接收信号的质量，并选择产生最佳信号质量的参数值。 在第一实施例中，通过分析表征由高速接收信号过采样得到的信号行为的数字眼来确定高速接收信号的质量。 在第二实施例中，通过分析用于数据采样的相位旋转器的行为来确定高速接收信号的质量。 最后，在第三实施例中，通过分析通过将相位旋转器的位置从一端移动到另一端而获得的数字眼，并且在每个位置处采样数据来确定高速接收信号的质量。