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20 条记录 (耗时 0.026 秒)

    Method to improve performance of a bipolar device using an amorphizing implant
    1.
    发明授权
    Method to improve performance of a bipolar device using an amorphizing implant 有权
    使用非晶化植入物改善双极器件性能的方法

    公开(公告)号：US07479438B2

    公开(公告)日：2009-01-20

    申请号：US11469032

    申请日：2006-08-31

    申请人： Alan S. Chen ,  Mark Dyson ,  Daniel C. Kerr ,  Nace M. Rossi

    发明人： Alan S. Chen ,  Mark Dyson ,  Daniel C. Kerr ,  Nace M. Rossi

    IPC分类号： H01L21/331 ,  H01L27/092

    CPC分类号： H01L21/8249 ,  H01L29/0821 ,  H01L29/732

    摘要： The invention, in one aspect, provides a semiconductor device that comprises a bipolar transistor located over and within a semiconductor substrate, a collector located within a tub of the bipolar transistor and having an amorphous region formed at least partially therein, a base located over the collector, and an emitter located over the base. There is also provided a method of fabricating the semiconductor device.

    摘要翻译： 本发明在一个方面提供了一种半导体器件，其包括位于半导体衬底之上和之内的双极晶体管，位于双极晶体管的桶内并具有至少部分形成在其中的非晶区域的集电体， 收集器和位于基座上方的发射器。 还提供了制造半导体器件的方法。

    Bipolar Device Having Improved Capacitance
    2.
    发明申请
    Bipolar Device Having Improved Capacitance 有权
    具有改善电容的双极器件

    公开(公告)号：US20080064177A1

    公开(公告)日：2008-03-13

    申请号：US11531477

    申请日：2006-09-13

    申请人： Alan S. Chen ,  Mark Dyson ,  Daniel C. Kerr ,  Nace M. Rossi

    发明人： Alan S. Chen ,  Mark Dyson ,  Daniel C. Kerr ,  Nace M. Rossi

    IPC分类号： H01L21/331

    CPC分类号： H01L29/7322 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0821 ,  H01L29/36 ,  H01L29/66272

    摘要： The invention, in one aspect, provides a semiconductor device that comprises a collector located in a semiconductor substrate and an isolation region located under the collector, wherein a peak dopant concentration of the isolation region is separated from a peak dopant concentration of the collector by at least about 0.9 microns. The invention also provides a method for forming this device.

    摘要翻译： 本发明在一个方面提供了一种半导体器件，其包括位于半导体衬底中的集电极和位于集电极下方的隔离区域，其中将隔离区域的峰值掺杂浓度与集电极的峰值掺杂浓度分开， 至少约0.9微米。 本发明还提供了一种用于形成该装置的方法。

    Method to Improve Performance of a Bipolar Device Using an Amorphizing Implant
    6.
    发明申请
    Method to Improve Performance of a Bipolar Device Using an Amorphizing Implant 有权
    使用非晶化植入物提高双极器件性能的方法

    公开(公告)号：US20080054406A1

    公开(公告)日：2008-03-06

    申请号：US11469032

    申请日：2006-08-31

    申请人： Alan S. Chen ,  Mark Dyson ,  Daniel C. Kerr ,  Nace M. Rossi

    发明人： Alan S. Chen ,  Mark Dyson ,  Daniel C. Kerr ,  Nace M. Rossi

    IPC分类号： H01L27/082

    CPC分类号： H01L21/8249 ,  H01L29/0821 ,  H01L29/732

    摘要： The invention, in one aspect, provides a semiconductor device that comprises a bipolar transistor located over and within a semiconductor substrate, a collector located within a tub of the bipolar transistor and having an amorphous region formed at least partially therein, a base located over the collector, and an emitter located over the base. There is also provided a method of fabricating the semiconductor device.

    摘要翻译： 本发明在一个方面提供了一种半导体器件，其包括位于半导体衬底之上和之内的双极晶体管，位于双极晶体管的桶内并具有至少部分形成在其中的非晶区域的集电体， 收集器和位于基座上方的发射器。 还提供了制造半导体器件的方法。

    Method to improve writer leakage in SiGe bipolar device
    7.
    发明授权
    Method to improve writer leakage in SiGe bipolar device 有权
    改善SiGe双极器件写入器泄漏的方法

    公开(公告)号：US07898038B2

    公开(公告)日：2011-03-01

    申请号：US12476994

    申请日：2009-06-02

    申请人： Alan S. Chen ,  Mark Dyson ,  Nace M. Rossi ,  Ranbir Singh

    发明人： Alan S. Chen ,  Mark Dyson ,  Nace M. Rossi ,  Ranbir Singh

    IPC分类号： H01L21/00

    CPC分类号： H01L21/8249 ,  H01L27/0623 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/7378 ,  Y10S438/969

    摘要： The invention, in one aspect, provides a method for fabricating a semiconductor device, which includes conducting an etch through an opening in an emitter layer to form a cavity from an underlying oxide layer that exposes a doped tub. A first silicon/germanium (SiGe) layer, which has a Ge concentration therein, is formed within the cavity and over the doped tub by adjusting a process parameter to induce a strain in the first SiGe layer. A second SiGe layer is formed over the first SiGe layer, and a capping layer is formed over the second SiGe layer.

    摘要翻译： 本发明在一个方面提供了一种用于制造半导体器件的方法，其包括通过发射极层中的开口进行蚀刻以从暴露掺杂的皿的下面的氧化物层形成空腔。 通过调整工艺参数以在第一SiGe层中引起应变，在空腔内和掺杂槽之上形成其中具有Ge浓度的第一硅/锗（SiGe）层。 在第一SiGe层上形成第二SiGe层，并且在第二SiGe层上形成覆盖层。

    METHOD TO IMPROVE WRITER LEAKAGE IN SiGe BIPOLAR DEVICE
    8.
    发明申请
    METHOD TO IMPROVE WRITER LEAKAGE IN SiGe BIPOLAR DEVICE 有权
    改善SiGe双极器件写入漏电的方法

    公开(公告)号：US20090236668A1

    公开(公告)日：2009-09-24

    申请号：US12476994

    申请日：2009-06-02

    申请人： Alan S. Chen ,  Mark Dyson ,  Nace M. Rossi ,  Ranbir Singh

    发明人： Alan S. Chen ,  Mark Dyson ,  Nace M. Rossi ,  Ranbir Singh

    IPC分类号： H01L27/102

    CPC分类号： H01L21/8249 ,  H01L27/0623 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/7378 ,  Y10S438/969

    摘要： The invention, in one aspect, provides a method for fabricating a semiconductor device, which includes conducting an etch through an opening in an emitter layer to form a cavity from an underlying oxide layer that exposes a doped tub. A first silicon/germanium (SiGe) layer, which has a Ge concentration therein, is formed within the cavity and over the doped tub by adjusting a process parameter to induce a strain in the first SiGe layer. A second SiGe layer is formed over the first SiGe layer, and a capping layer is formed over the second SiGe layer.

    摘要翻译： 本发明在一个方面提供了一种用于制造半导体器件的方法，其包括通过发射极层中的开口进行蚀刻以从暴露掺杂的皿的下面的氧化物层形成空腔。 通过调整工艺参数以在第一SiGe层中引起应变，在空腔内和掺杂槽之上形成其中具有Ge浓度的第一硅/锗（SiGe）层。 在第一SiGe层上形成第二SiGe层，并且在第二SiGe层上形成覆盖层。

    Method to Reduce Boron Penetration in a SiGe Bipolar Device
    9.
    发明申请
    Method to Reduce Boron Penetration in a SiGe Bipolar Device 有权
    减少SiGe双极器件中硼渗透的方法

    公开(公告)号：US20080237642A1

    公开(公告)日：2008-10-02

    申请号：US11694021

    申请日：2007-03-30

    申请人： Alan S. Chen ,  Mark Dyson ,  Nace M. Rossi ,  Ranbir Singh ,  Xiaojun Yuan

    发明人： Alan S. Chen ,  Mark Dyson ,  Nace M. Rossi ,  Ranbir Singh ,  Xiaojun Yuan

    IPC分类号： H01L29/737

    CPC分类号： H01L29/7378 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/66242

    摘要： The invention, in one aspect, provides a method of manufacturing a semiconductor device. This aspect includes forming gate electrodes in a non-bipolar transistor region of a semiconductor substrate, placing a polysilicon layer over the gate electrodes in the non-bipolar transistor region and over the semiconductor substrate within a bipolar transistor region. A protective layer is formed over the polysilicon layer. The protective layer has a weight percent of hydrogen that is less than about 9% and is selective to silicon germanium (SiGe), such that SiGe does not form on the protective layer. This aspect further includes forming emitters for bipolar transistors in the bipolar transistor region, including forming a SiGe layer under a portion of the polysilicon layer.

    摘要翻译： 本发明在一个方面提供一种制造半导体器件的方法。 该方面包括在半导体衬底的非双极晶体管区域中形成栅电极，将多晶硅层放置在非双极晶体管区域中的栅电极之上，并在双极晶体管区域内的半导体衬底上。 在多晶硅层上形成保护层。 保护层具有小于约9％的氢的重量百分数，并且对硅锗（SiGe）是选择性的，使得SiGe不在保护层上形成。 该方面还包括在双极晶体管区域中形成用于双极晶体管的发射极，包括在多晶硅层的一部分下形成SiGe层。