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    METHOD TO REDUCE BORON PENETRATION IN A SiGe BIPOLAR DEVICE
    1.
    发明申请
    METHOD TO REDUCE BORON PENETRATION IN A SiGe BIPOLAR DEVICE 审中-公开
    降低SiGe双极器件中硼孔渗透的方法

    公开(公告)号：US20090050977A1

    公开(公告)日：2009-02-26

    申请号：US12256677

    申请日：2008-10-23

    申请人： Alan S. Chen ,  Mark Dyson ,  Nace M. Rossi ,  Ranbir Singh ,  Xiaojun Yuan

    发明人： Alan S. Chen ,  Mark Dyson ,  Nace M. Rossi ,  Ranbir Singh ,  Xiaojun Yuan

    IPC分类号： H01L27/06

    CPC分类号： H01L29/7378 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/66242

    摘要： The invention, in one aspect, provides a method of manufacturing a semiconductor device. This aspect includes forming gate electrodes in a non-bipolar transistor region of a semiconductor substrate, placing a polysilicon layer over the gate electrodes in the non-bipolar transistor region and over the semiconductor substrate within a bipolar transistor region. A protective layer is formed over the polysilicon layer. The protective layer has a weight percent of hydrogen that is less than about 9% and is selective to silicon germanium (SiGe), such that SiGe does not form on the protective layer. This aspect further includes forming emitters for bipolar transistors in the bipolar transistor region, including forming a SiGe layer under a portion of the polysilicon layer.

    摘要翻译： 本发明在一个方面提供一种制造半导体器件的方法。 该方面包括在半导体衬底的非双极晶体管区域中形成栅电极，将多晶硅层放置在非双极晶体管区域中的栅电极之上，并在双极晶体管区域内的半导体衬底上。 在多晶硅层上形成保护层。 保护层具有小于约9％的氢的重量百分数，并且对硅锗（SiGe）是选择性的，使得SiGe不在保护层上形成。 该方面还包括在双极晶体管区域中形成用于双极晶体管的发射极，包括在多晶硅层的一部分下形成SiGe层。

    Method to reduce boron penetration in a SiGe bipolar device
    4.
    发明授权
    Method to reduce boron penetration in a SiGe bipolar device 有权
    降低SiGe双极器件中硼渗透的方法

    公开(公告)号：US07456061B2

    公开(公告)日：2008-11-25

    申请号：US11694021

    申请日：2007-03-30

    申请人： Alan S. Chen ,  Mark Dyson ,  Nace M. Rossi ,  Ranbir Singh ,  Xiaojun Yuan

    发明人： Alan S. Chen ,  Mark Dyson ,  Nace M. Rossi ,  Ranbir Singh ,  Xiaojun Yuan

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/7378 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/66242

    摘要： The invention, in one aspect, provides a method of manufacturing a semiconductor device. This aspect includes forming gate electrodes in a non-bipolar transistor region of a semiconductor substrate, placing a polysilicon layer over the gate electrodes in the non-bipolar transistor region and over the semiconductor substrate within a bipolar transistor region. A protective layer is formed over the polysilicon layer. The protective layer has a weight percent of hydrogen that is less than about 9% and is selective to silicon germanium (SiGe), such that SiGe does not form on the protective layer. This aspect further includes forming emitters for bipolar transistors in the bipolar transistor region, including forming a SiGe layer under a portion of the polysilicon layer.

    摘要翻译： 本发明在一个方面提供一种制造半导体器件的方法。 该方面包括在半导体衬底的非双极晶体管区域中形成栅电极，将多晶硅层放置在非双极晶体管区域中的栅电极之上，并在双极晶体管区域内的半导体衬底上。 在多晶硅层上形成保护层。 保护层具有小于约9％的氢的重量百分数，并且对硅锗（SiGe）是选择性的，使得SiGe不在保护层上形成。 该方面还包括在双极晶体管区域中形成用于双极晶体管的发射极，包括在多晶硅层的一部分下形成SiGe层。

    Method to Reduce Boron Penetration in a SiGe Bipolar Device
    5.
    发明申请
    Method to Reduce Boron Penetration in a SiGe Bipolar Device 有权
    减少SiGe双极器件中硼渗透的方法

    公开(公告)号：US20080237642A1

    公开(公告)日：2008-10-02

    申请号：US11694021

    申请日：2007-03-30

    申请人： Alan S. Chen ,  Mark Dyson ,  Nace M. Rossi ,  Ranbir Singh ,  Xiaojun Yuan

    发明人： Alan S. Chen ,  Mark Dyson ,  Nace M. Rossi ,  Ranbir Singh ,  Xiaojun Yuan

    IPC分类号： H01L29/737

    CPC分类号： H01L29/7378 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/66242

    摘要： The invention, in one aspect, provides a method of manufacturing a semiconductor device. This aspect includes forming gate electrodes in a non-bipolar transistor region of a semiconductor substrate, placing a polysilicon layer over the gate electrodes in the non-bipolar transistor region and over the semiconductor substrate within a bipolar transistor region. A protective layer is formed over the polysilicon layer. The protective layer has a weight percent of hydrogen that is less than about 9% and is selective to silicon germanium (SiGe), such that SiGe does not form on the protective layer. This aspect further includes forming emitters for bipolar transistors in the bipolar transistor region, including forming a SiGe layer under a portion of the polysilicon layer.

    摘要翻译： 本发明在一个方面提供一种制造半导体器件的方法。 该方面包括在半导体衬底的非双极晶体管区域中形成栅电极，将多晶硅层放置在非双极晶体管区域中的栅电极之上，并在双极晶体管区域内的半导体衬底上。 在多晶硅层上形成保护层。 保护层具有小于约9％的氢的重量百分数，并且对硅锗（SiGe）是选择性的，使得SiGe不在保护层上形成。 该方面还包括在双极晶体管区域中形成用于双极晶体管的发射极，包括在多晶硅层的一部分下形成SiGe层。

    Method to improve writer leakage in SiGe bipolar device
    6.
    发明授权
    Method to improve writer leakage in SiGe bipolar device 有权
    改善SiGe双极器件写入器泄漏的方法

    公开(公告)号：US07898038B2

    公开(公告)日：2011-03-01

    申请号：US12476994

    申请日：2009-06-02

    申请人： Alan S. Chen ,  Mark Dyson ,  Nace M. Rossi ,  Ranbir Singh

    发明人： Alan S. Chen ,  Mark Dyson ,  Nace M. Rossi ,  Ranbir Singh

    IPC分类号： H01L21/00

    CPC分类号： H01L21/8249 ,  H01L27/0623 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/7378 ,  Y10S438/969

    摘要： The invention, in one aspect, provides a method for fabricating a semiconductor device, which includes conducting an etch through an opening in an emitter layer to form a cavity from an underlying oxide layer that exposes a doped tub. A first silicon/germanium (SiGe) layer, which has a Ge concentration therein, is formed within the cavity and over the doped tub by adjusting a process parameter to induce a strain in the first SiGe layer. A second SiGe layer is formed over the first SiGe layer, and a capping layer is formed over the second SiGe layer.

    摘要翻译： 本发明在一个方面提供了一种用于制造半导体器件的方法，其包括通过发射极层中的开口进行蚀刻以从暴露掺杂的皿的下面的氧化物层形成空腔。 通过调整工艺参数以在第一SiGe层中引起应变，在空腔内和掺杂槽之上形成其中具有Ge浓度的第一硅/锗（SiGe）层。 在第一SiGe层上形成第二SiGe层，并且在第二SiGe层上形成覆盖层。

    Method to improve writer leakage in a SiGe bipolar device
    7.
    发明授权
    Method to improve writer leakage in a SiGe bipolar device 有权
    改善SiGe双极器件写入器泄漏的方法

    公开(公告)号：US07557010B2

    公开(公告)日：2009-07-07

    申请号：US11673645

    申请日：2007-02-12

    申请人： Alan S. Chen ,  Mark Dyson ,  Nace M. Rossi ,  Ranbir Singh

    发明人： Alan S. Chen ,  Mark Dyson ,  Nace M. Rossi ,  Ranbir Singh

    IPC分类号： H01L21/20

    CPC分类号： H01L21/8249 ,  H01L27/0623 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/7378 ,  Y10S438/969

    摘要： The invention, in one aspect, provides a method for fabricating a semiconductor device, which includes conducting an etch through an opening in an emitter layer to form a cavity from an underlying oxide layer that exposes a doped tub. A first silicon/germanium (SiGe) layer, which has a Ge concentration therein, is formed within the cavity and over the doped tub by adjusting a process parameter to induce a strain in the first SiGe layer. A second SiGe layer is formed over the first SiGe layer, and a capping layer is formed over the second SiGe layer.

    摘要翻译： 本发明在一个方面提供了一种用于制造半导体器件的方法，其包括通过发射极层中的开口进行蚀刻以从暴露掺杂的皿的下面的氧化物层形成空腔。 通过调整工艺参数以在第一SiGe层中引起应变，在空腔内和掺杂槽之上形成其中具有Ge浓度的第一硅/锗（SiGe）层。 在第一SiGe层上形成第二SiGe层，并且在第二SiGe层上形成覆盖层。

    Method to Improve Writer Leakage in a SiGe Bipolar Device
    8.
    发明申请
    Method to Improve Writer Leakage in a SiGe Bipolar Device 有权
    提高SiGe双极器件中写入器泄漏的方法

    公开(公告)号：US20080191246A1

    公开(公告)日：2008-08-14

    申请号：US11673645

    申请日：2007-02-12

    申请人： Alan S. Chen ,  Mark Dyson ,  Nace M. Rossi ,  Ranbir Singh

    发明人： Alan S. Chen ,  Mark Dyson ,  Nace M. Rossi ,  Ranbir Singh

    IPC分类号： H01L21/8249 ,  H01L21/331 ,  H01L29/737

    CPC分类号： H01L21/8249 ,  H01L27/0623 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/7378 ,  Y10S438/969

    摘要： The invention, in one aspect, provides a method for fabricating a semiconductor device, which includes conducting an etch through an opening in an emitter layer to form a cavity from an underlying oxide layer that exposes a doped tub. A first silicon/germanium (SiGe) layer, which has a Ge concentration therein, is formed within the cavity and over the doped tub by adjusting a process parameter to induce a strain in the first SiGe layer. A second SiGe layer is formed over the first SiGe layer, and a capping layer is formed over the second SiGe layer.

    摘要翻译： 本发明在一个方面提供了一种用于制造半导体器件的方法，其包括通过发射极层中的开口进行蚀刻以从暴露掺杂的皿的下面的氧化物层形成空腔。 通过调整工艺参数以在第一SiGe层中引起应变，在空腔内和掺杂槽之上形成其中具有Ge浓度的第一硅/锗（SiGe）层。 在第一SiGe层上形成第二SiGe层，并且在第二SiGe层上形成覆盖层。

    METHOD TO IMPROVE WRITER LEAKAGE IN SiGe BIPOLAR DEVICE
    9.
    发明申请
    METHOD TO IMPROVE WRITER LEAKAGE IN SiGe BIPOLAR DEVICE 有权
    改善SiGe双极器件写入漏电的方法

    公开(公告)号：US20090236668A1

    公开(公告)日：2009-09-24

    申请号：US12476994

    申请日：2009-06-02

    申请人： Alan S. Chen ,  Mark Dyson ,  Nace M. Rossi ,  Ranbir Singh

    发明人： Alan S. Chen ,  Mark Dyson ,  Nace M. Rossi ,  Ranbir Singh

    IPC分类号： H01L27/102

    CPC分类号： H01L21/8249 ,  H01L27/0623 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/7378 ,  Y10S438/969

    摘要： The invention, in one aspect, provides a method for fabricating a semiconductor device, which includes conducting an etch through an opening in an emitter layer to form a cavity from an underlying oxide layer that exposes a doped tub. A first silicon/germanium (SiGe) layer, which has a Ge concentration therein, is formed within the cavity and over the doped tub by adjusting a process parameter to induce a strain in the first SiGe layer. A second SiGe layer is formed over the first SiGe layer, and a capping layer is formed over the second SiGe layer.

    摘要翻译： 本发明在一个方面提供了一种用于制造半导体器件的方法，其包括通过发射极层中的开口进行蚀刻以从暴露掺杂的皿的下面的氧化物层形成空腔。 通过调整工艺参数以在第一SiGe层中引起应变，在空腔内和掺杂槽之上形成其中具有Ge浓度的第一硅/锗（SiGe）层。 在第一SiGe层上形成第二SiGe层，并且在第二SiGe层上形成覆盖层。

    Method to reduce trench capacitor leakage for random access memory device
    10.
    发明授权
    Method to reduce trench capacitor leakage for random access memory device 有权

    公开(公告)号：US08367497B2

    公开(公告)日：2013-02-05

    申请号：US12680017

    申请日：2007-10-31

    申请人： Nace M. Rossi ,  Ranbir Singh ,  Xiaojun Yuan

    发明人： Nace M. Rossi ,  Ranbir Singh ,  Xiaojun Yuan

    IPC分类号： H01L21/8242 ,  H01L27/108

    摘要： A method is provided that includes forming a trench isolation structure in a dynamic random memory region (DRAM) of a substrate and patterning an etch mask over the trench structure to expose a portion of the trench structure. A portion of the exposed trench structure is removed to form a gate trench that includes a first corner formed by the substrate and a second corner formed by the trench structure. The etch mask is removed and the first corner of the gate trench is rounded to form a rounded corner. This is followed by the formation of an oxide layer over a sidewall of the gate trench, the first rounded corner, and the semiconductor substrate adjacent the gate trench. The trench is filled with a gate material.