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1.发明授权Methods and systems for implementing logic gates with spintronic devices located at nanowire crossbar junctions of crossbar arrays 有权用于实现位于横杆阵列的纳米线交叉点处的自旋电子器件的逻辑门的方法和系统公开(公告)号：US08143682B2
公开(公告)日：2012-03-27
申请号：US11590959
申请日：2006-10-31
IPC分类号： H01L29/82
摘要： Various method and system embodiments of the present invention are directed to implementing serial logic gates using nanowire-crossbar arrays with spintronic devices located at nanowire-crossbar junctions. In one embodiment of the present invention, a nanowire-crossbar array comprises a first nanowire and a number of substantially parallel control nanowires positioned so that each control nanowire overlaps the first nanowire. The nanowire-crossbar array includes a number of spintronic devices. Each spintronic device is configured to connect one of the control nanowires to the first nanowire and operate as a latch for controlling signal transmissions between the control nanowire and the first nanowire.
摘要翻译： 本发明的各种方法和系统实施例涉及使用位于纳米线交叉点处的自旋电子器件的纳米线交叉阵列来实现串行逻辑门。 在本发明的一个实施例中，纳米线交叉串阵列包括第一纳米线和多个基本上平行的控制纳米线，所述纳米线被定位成使得每个对照纳米线与第一纳米线重叠。 纳米线交叉开关阵列包括许多自旋电子器件。 每个自旋电子设备被配置为将控制纳米线中的一个连接到第一纳米线并且用作用于控制控制纳米线和第一纳米线之间的信号传输的锁存器。
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2.发明申请Methods and systems for implementing logic gates with spintronic devices located at nanowire crossbar junctions of crossbar arrays 有权用于实现位于横杆阵列的纳米线交叉点处的自旋电子器件的逻辑门的方法和系统公开(公告)号：US20080100345A1
公开(公告)日：2008-05-01
申请号：US11590959
申请日：2006-10-31
IPC分类号： H03K19/20
摘要： Various method and system embodiments of the present invention are directed to implementing serial logic gates using nanowire-crossbar arrays with spintronic devices located at nanowire-crossbar junctions. In one embodiment of the present invention, a nanowire-crossbar array comprises a first nanowire and a number of substantially parallel control nanowires positioned so that each control nanowire overlaps the first nanowire. The nanowire-crossbar array includes a number of spintronic devices. Each spintronic device is configured to connect one of the control nanowires to the first nanowire and operate as a latch for controlling signal transmissions between the control nanowire and the first nanowire.
摘要翻译： 本发明的各种方法和系统实施例涉及使用位于纳米线交叉点处的自旋电子器件的纳米线交叉阵列来实现串行逻辑门。 在本发明的一个实施例中，纳米线交叉串阵列包括第一纳米线和多个基本上平行的控制纳米线，所述纳米线被定位成使得每个对照纳米线与第一纳米线重叠。 纳米线交叉开关阵列包括许多自旋电子器件。 每个自旋电子设备被配置为将控制纳米线中的一个连接到第一纳米线并且用作用于控制控制纳米线和第一纳米线之间的信号传输的锁存器。
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3.发明申请Three-dimensional crossbar array systems and methods for writing information to and reading information stored in three-dimensional crossbar array junctions 有权用于将信息写入和读取存储在三维交叉列阵列结点中的信息的三维交叉列阵列系统和方法公开(公告)号：US20080237886A1
公开(公告)日：2008-10-02
申请号：US11729228
申请日：2007-03-28
申请人： Wei Wu , R. Stanley Williams , Warren Robinett , Gregory S. Snider , Zhaoning Yu , Shih-Yuan Wang , Duncan Stewart
发明人： Wei Wu , R. Stanley Williams , Warren Robinett , Gregory S. Snider , Zhaoning Yu , Shih-Yuan Wang , Duncan Stewart
IPC分类号： H01L23/48
CPC分类号： H01L27/101 , B82Y10/00 , G11C13/00 , G11C13/0023 , G11C13/0033 , G11C2213/71 , G11C2213/79 , G11C2213/81 , H01L2924/0002 , Y10S977/762 , H01L2924/00
摘要： Various embodiments of the present invention are directed to three-dimensional crossbar arrays. In one aspect of the present invention, a three-dimensional crossbar array includes a plurality of crossbar arrays, a first demultiplexer, a second demultiplexer, and a third demultiplexer. Each crossbar array includes a first layer of nanowires, a second layer of nanowires overlaying the first layer of nanowires, and a third layer of nanowires overlaying the second layer of nanowires. The first demultiplexer is configured to address nanowires in the first layer of nanowires of each crossbar array, the second demultiplexer is configured to address nanowires in the second layer of nanowires of each crossbar array, and the third demultiplexer is configured to supply a signal to the nanowires in the third layer of nanowires of each crossbar array.
摘要翻译： 本发明的各种实施例涉及三维横杆阵列。 在本发明的一个方面，三维交叉开关阵列包括多个交叉开关阵列，第一解复用器，第二解复用器和第三解复用器。 每个横杆阵列包括第一纳米线层，覆盖第一纳米线层的第二纳米线层和覆盖第二纳米线层的第三层纳米线。 第一解复用器被配置为寻址每个交叉列阵列的纳米线的第一层中的纳米线，第二解复用器被配置为寻址每个交叉列阵列的第二纳米线层中的纳米线，并且第三解复用器被配置为向 纳米线在每个交叉列阵列的第三层纳米线中。
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4.发明授权Three-dimensional crossbar array systems and methods for writing information to and reading information stored in three-dimensional crossbar array junctions 有权用于将信息写入和读取存储在三维交叉列阵列结点中的信息的三维交叉列阵列系统和方法公开(公告)号：US07763978B2
公开(公告)日：2010-07-27
申请号：US11729228
申请日：2007-03-28
申请人： Wei Wu , R. Stanley Williams , Warren Robinett , Gregory S. Snider , Zhaoning Yu , Shih-Yuan Wang , Duncan Stewart
发明人： Wei Wu , R. Stanley Williams , Warren Robinett , Gregory S. Snider , Zhaoning Yu , Shih-Yuan Wang , Duncan Stewart
CPC分类号： H01L27/101 , B82Y10/00 , G11C13/00 , G11C13/0023 , G11C13/0033 , G11C2213/71 , G11C2213/79 , G11C2213/81 , H01L2924/0002 , Y10S977/762 , H01L2924/00
摘要： Various embodiments of the present invention are directed to three-dimensional crossbar arrays. In one aspect of the present invention, a three-dimensional crossbar array includes a plurality of crossbar arrays, a first demultiplexer, a second demultiplexer, and a third demultiplexer. Each crossbar array includes a first layer of nanowires, a second layer of nanowires overlaying the first layer of nanowires, and a third layer of nanowires overlaying the second layer of nanowires. The first demultiplexer is configured to address nanowires in the first layer of nanowires of each crossbar array, the second demultiplexer is configured to address nanowires in the second layer of nanowires of each crossbar array, and the third demultiplexer is configured to supply a signal to the nanowires in the third layer of nanowires of each crossbar array.
摘要翻译： 本发明的各种实施例涉及三维横杆阵列。 在本发明的一个方面，三维交叉开关阵列包括多个交叉开关阵列，第一解复用器，第二解复用器和第三解复用器。 每个横杆阵列包括第一纳米线层，覆盖第一纳米线层的第二纳米线层和覆盖第二纳米线层的第三层纳米线。 第一解复用器被配置为寻址每个交叉列阵列的纳米线的第一层中的纳米线，第二解复用器被配置为寻址每个交叉列阵列的第二纳米线层中的纳米线，并且第三解复用器被配置为向 纳米线在每个交叉列阵列的第三层纳米线中。
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公开(公告)号：US08605488B2
公开(公告)日：2013-12-10
申请号：US13256239
申请日：2009-06-12
IPC分类号： G11C11/24
CPC分类号： G11C13/00 , G11C11/24 , G11C23/00 , G11C2207/066
摘要： A capacitive crossbar array includes a first set of conductors and a second set of conductors which intersect to form crosspoints. A nonlinear capacitive device is interposed between a first conductor within the first set and a second conductor within the second set at a crosspoint. The nonlinear capacitive device is configured to store information which is accessible through said first conductor and said second conductor. A method for utilizing a capacitive crossbar array is also provided.
摘要翻译： 电容式交叉开关阵列包括第一组导体和第二组导体，其相交以形成交叉点。 非线性电容性装置插入在第一组内的第一导体和第二组中的交叉点处的第二导体之间。 非线性电容性装置被配置为存储可通过所述第一导体和所述第二导体访问的信息。 还提供了一种用于使用电容式交叉开关阵列的方法。
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公开(公告)号：US20120014170A1
公开(公告)日：2012-01-19
申请号：US13256239
申请日：2009-06-12
IPC分类号： G11C11/24
CPC分类号： G11C13/00 , G11C11/24 , G11C23/00 , G11C2207/066
摘要： A capacitive crossbar array (100) includes a first set of conductors (102) and a second set of conductors (104) which intersect to form crosspoints. A nonlinear capacitive device (106) is interposed between a first conductor (103) within the first set (102) and a second conductor (105) within the second set (104) at a crosspoint. The nonlinear capacitive device (106) is configured to store information which is accessible through said first conductor (103) and said second conductor (105). A method for utilizing a capacitive crossbar array (100) is also provided.
摘要翻译： 电容纵横阵列（100）包括第一组导体（102）和第二组导体（104），其相交以形成交叉点。 在第一组（102）内的第一导体（103）与第二组（104）内的第二导体（105）之间的交叉点处插入非线性电容性装置（106）。 非线性电容性装置（106）被配置为存储可通过所述第一导体（103）和所述第二导体（105）访问的信息。 还提供了一种用于使用电容式交叉开关阵列（100）的方法。
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公开(公告)号：US07692215B2
公开(公告)日：2010-04-06
申请号：US11701086
申请日：2007-01-31
CPC分类号： H01L29/0665 , B82Y10/00 , G11C2213/81 , H01H1/0094 , H01L27/285 , H01L29/0673 , H01L29/0676 , H01L51/0591 , H01L51/0595
摘要： Embodiments of the present invention are directed to mixed-scale electronic interfaces, included in integrated circuits and other electronic devices, that provide for dense electrical interconnection between microscale features of a predominantly microscale or submicroscale layer and nanoscale features of a predominantly nanoscale layer. The predominantly nanoscale layer, in one embodiment of the present invention, comprises a tessellated pattern of submicroscale or microscale pads densely interconnected by nanowire junctions between sets of parallel, closely spaced nanowire bundles. The predominantly submicroscale or microscale layer includes pins positioned complementarily to the submicroscale or microscale pads in the predominantly nanoscale layer. Pins can be configured according to any periodic tiling of the microscale layer.
摘要翻译： 本发明的实施例涉及包括在集成电路和其他电子设备中的混合比例电子接口，其提供主要是微米级或亚微米级的微尺度特征之间的密集电互连以及主要为纳米尺度层的纳米尺度特征。 在本发明的一个实施方案中，主要是纳米尺度层包括通过平行的，紧密间隔的纳米线束组之间的纳米线结密合地互连的亚微米级或微米级的镶嵌图案。 主要是亚微米级或微尺度层包括与主要是纳米级层中的亚微米级或微尺度焊盘互补定位的引脚。 引脚可以根据微层的任何周期性平铺进行配置。
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公开(公告)号：US07544977B2
公开(公告)日：2009-06-09
申请号：US11342076
申请日：2006-01-27
CPC分类号： H01L29/0665 , B82Y10/00 , G11C2213/81 , H01H1/0094 , H01L27/285 , H01L29/0673 , H01L29/0676 , H01L51/0591 , H01L51/0595
摘要： Embodiments of the present invention are directed to mixed-scale electronic interfaces, included in integrated circuits and other electronic devices, that provide for dense electrical interconnection between microscale features of a predominantly microscale or submicroscale layer and nanoscale features of a predominantly nanoscale layer. The predominantly nanoscale layer, in one embodiment of the present invention, comprises a tessellated pattern of submicroscale or microscale pads densely interconnected by nanowire junctions between sets of parallel, closely spaced nanowire bundles. The predominantly submicroscale or microscale layer includes pins positioned complementarily to the submicroscale or microscale pads in the predominantly nanoscale layer.
摘要翻译： 本发明的实施例涉及包括在集成电路和其他电子设备中的混合比例电子接口，其提供主要是微米级或亚微米级的微尺度特征之间的密集电互连以及主要为纳米尺度层的纳米尺度特征。 在本发明的一个实施方案中，主要是纳米尺度层包括通过平行的，紧密间隔的纳米线束组之间的纳米线结密合地互连的亚微米级或微米级的镶嵌图案。 主要是亚微米级或微尺度层包括与主要是纳米级层中的亚微米级或微尺度焊盘互补定位的引脚。
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公开(公告)号：US07833842B2
公开(公告)日：2010-11-16
申请号：US12630076
申请日：2009-12-03
IPC分类号： H01L21/82
CPC分类号： H01L29/0665 , B82Y10/00 , G11C2213/81 , H01H1/0094 , H01L27/285 , H01L29/0673 , H01L29/0676 , H01L51/0591 , H01L51/0595
摘要： Embodiments of the present invention are directed to mixed-scale electronic interfaces, included in integrated circuits and other electronic devices, that provide for dense electrical interconnection between microscale features of a predominantly microscale or submicroscale layer and nanoscale features of a predominantly nanoscale layer. A method is provided for fabricating a nanoscale/microscale interface having a microscale layer and a predominantly nanoscale layer.
摘要翻译： 本发明的实施例涉及包括在集成电路和其他电子设备中的混合比例电子接口，其提供主要是微米级或亚微米级的微尺度特征之间的密集电互连以及主要为纳米尺度层的纳米尺度特征。 提供了一种用于制造具有微米级和主要为纳米尺度层的纳米尺度/微米界面的方法。
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公开(公告)号：US20100081238A1
公开(公告)日：2010-04-01
申请号：US12630076
申请日：2009-12-03
IPC分类号： H01L21/77
CPC分类号： H01L29/0665 , B82Y10/00 , G11C2213/81 , H01H1/0094 , H01L27/285 , H01L29/0673 , H01L29/0676 , H01L51/0591 , H01L51/0595
摘要： Embodiments of the present invention are directed to mixed-scale electronic interfaces, included in integrated circuits and other electronic devices, that provide for dense electrical interconnection between microscale features of a predominantly microscale or submicroscale layer and nanoscale features of a predominantly nanoscale layer. A method is provided for fabricating a nanoscale/microscale interface having a microscale layer and a predominantly nanoscale layer.
摘要翻译： 本发明的实施例涉及包括在集成电路和其他电子设备中的混合比例电子接口，其提供主要是微米级或亚微米级的微尺度特征之间的密集电互连以及主要为纳米尺度层的纳米尺度特征。 提供了一种用于制造具有微米级和主要为纳米尺度层的纳米尺度/微米界面的方法。
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