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1.发明授权Data processing apparatus for dynamically setting timings in a dynamic memory system 失效用于在动态存储器系统中动态地设置定时的数据处理装置
公开(公告)号：US5522064A
公开(公告)日：1996-05-28
申请号：US590978
申请日：1990-10-01
IPC分类号： G11C11/401 , G06F12/00 , G06F12/02 , G06F12/06 , G06F13/42 , G11C11/407 , G06F1/06 , G06F1/04 , G06F1/08
CPC分类号： G06F13/4243
摘要： A data processing system includes a memory controller for accessing a dynamic memory having a plurality of SIMMs (Single In-line Memory Modules) that differ in size and speed of operation. The memory controller is operable, in response to an access request for a given SIMM, to read from a SIMM definition register and dynamically produce memory access signals in accordance with the timing requirements of the particular SIMM being accessed. Such signals are set each time a SIMM is accessed. The signals provide different clock periods of RAS precharge time, RAS (Row Address Strobe) to CAS (Column Address Strobe) time, and CAS pulse width, depending on the SIMM being accessed.
摘要翻译： 数据处理系统包括存储器控制器，用于访问动态存储器，该动态存储器具有大小和操作速度不同的多个SIMM（单列直插存储器模块）。 响应于给定SIMM的访问请求，存储器控制器可操作地从SIMM定义寄存器读取并且根据所访问的特定SIMM的定时要求动态地产生存储器访问信号。 每次访问SIMM时都会设置这些信号。 这些信号根据正在访问的SIMM提供RAS预充电时间，RAS（行地址选通）到CAS（列地址选通）时间的不同时钟周期和CAS脉冲宽度。
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2.发明授权Data processing system including a memory controller for direct or interleave memory accessing 失效数据处理系统，包括用于直接或间接存储器访问的存储器控制器
公开(公告)号：US5226134A
公开(公告)日：1993-07-06
申请号：US591306
申请日：1990-10-01
CPC分类号： G11C8/12 , G06F12/0607
摘要： A data processing system includes a processor for accessing a memory in either a direct mode or an indirect mode. The memory includes at least two memory banks and two decoders for decoding bank addresses. The decoders produce bank select signals. In direct mode, the decoder outputs are generated according to which bank is addressed. In interleave mode, the two decoder outputs are ANDed to select both banks covering the address range of the selected banks.
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3.发明授权Method and structure for providing error correction code for 8-byte data words on SIMM cards 失效在SIMM卡上为8字节数据字提供纠错码的方法和结构
公开(公告)号：US5481552A
公开(公告)日：1996-01-02
申请号：US177078
申请日：1993-12-30
CPC分类号： G06F11/1056
摘要： The present invention relates to a method and structure for implementing a 64/8 ECC algorithm on a SIMM using a computer which has a 32-bit bus and is configured with a 36-bit wide memory. This is accomplished by writing two successive 4 byte words from the system to latches, to form an 8 byte quad word, and writing 8 check bits utilizing the entire 64 bits of the quad word. One-half of the quad word (i.e., 32 bits) together with 4 of the 8 check bits for a total of 36 bits is stored at one address location in memory, and the remaining 32 bits of the quad word, together with the remaining 4 check bits, are stored at another, preferably the successive 36 bit, address location in memory. When the quad word and check bits are read from the memory, they are read serially, i.e., the first 32 bits and 4 associated check bits are read and latched, followed by the second 32 bits and the 4 associated check bits being read and combined with the first 32 bits of data and 4 check bits so as to essentially "reconstitute" the original 64-bit quad word with 8 check bits. From the "reconstituted" 64-bit data word and 8 check bits, the error correction is performed. The 64-bit quad word with the corrected data is latched and asserted successively on the data bus as two 32-bit words. Also, preferably logic and circuitry to perform a read-modify-write (R-M-W) function are provided.
摘要翻译： 本发明涉及一种使用具有32位总线并配置有36位宽存储器的计算机在SIMM上实现64/8 ECC算法的方法和结构。 这是通过从系统中写入两个连续的4个字节字来锁存，形成一个8字节的四字，以及使用四字的整个64位写入8个校验位来实现的。 四位字的一半（即32位）与总共36位的8个校验位中的4个存储在存储器中的一个地址位置，剩余的32位的四位字与剩余的 4个校验位存储在存储器中的另一个，优选地是连续的36位地址位置。 当从存储器中读取四位字和校验位时，它们被连续读取，即读取和锁存前32位和4位相关联的校验位，随后读取和组合第二个32位和4个相关联的校验位 具有前32位数据和4个校验位，以便基本上“重构”具有8个校验位的原始64位四位字。 从“重构”的64位数据字和8个校验位执行纠错。 具有校正数据的64位四位字在数据总线上被连续地锁存和断言为两个32位字。 此外，优选地提供用于执行读 - 修改 - 写（R-M-W）功能的逻辑和电路。
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公开(公告)号：US09094162B2
公开(公告)日：2015-07-28
申请号：US13524804
申请日：2012-06-15
CPC分类号： H04L1/0045 , H03M13/09 , H03M13/098 , H03M13/2906 , H03M13/2927 , H04L1/0061
摘要： Error detection and correction of a data transmission, including: receiving a block of data, where the block includes a predefined number of words, with each word including a parity bit, where the block of data also an error-correcting code (ECC); determining, for each word in dependence upon the parity bit of the word, whether the word of the block includes a parity error; committing each word that does not include a parity error, if only one word of the block includes a parity error: correcting the one word that includes the parity error through use of the ECC of the block and committing the corrected word.
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公开(公告)号：US20130159810A1
公开(公告)日：2013-06-20
申请号：US13326805
申请日：2011-12-15
CPC分类号： H04L1/0045 , H03M13/09 , H03M13/098 , H03M13/2906 , H03M13/2927 , H04L1/0061
摘要： Error detection and correction of a data transmission, including: receiving a block of data, where the block includes a predefined number of words, with each word including a parity bit, where the block of data also an error-correcting code (ECC); determining, for each word in dependence upon the parity bit of the word, whether the word of the block includes a parity error; committing each word that does not include a parity error, if only one word of the block includes a parity error: correcting the one word that includes the parity error through use of the ECC of the block and committing the corrected word.
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公开(公告)号：US07493503B2
公开(公告)日：2009-02-17
申请号：US11315837
申请日：2005-12-22
申请人： Alfredo Aldereguia , Brian E. Bigelow , Dhruv M. Desai , Scott N. Dunham , Nickolas J. Gruendler , William G. Holland , James E. Hughes , Randolph S. Kolvick , Challis L. Purrington , Michael L. Scollard , Gary R. Shippy
发明人： Alfredo Aldereguia , Brian E. Bigelow , Dhruv M. Desai , Scott N. Dunham , Nickolas J. Gruendler , William G. Holland , James E. Hughes , Randolph S. Kolvick , Challis L. Purrington , Michael L. Scollard , Gary R. Shippy
IPC分类号： G06F1/26
CPC分类号： G06F1/3209
摘要： A method and system are disclosed to enable and control power reduction in a blade/chassis system. A “maximum power reduction” attribute is stored in the VPD of the blade (or can otherwise be input to or retrieved or calculated by the management entity). The management module of the chassis in which the blades and power supplies are located uses this information to manage the power reduction of blades when the system is operating in an over-subscription mode and a power supply fails. If throttling is required, the system knows the amount of power reduction available for each blade and controls the throttling by spreading it out among the blades in the system so that, ideally, no blade will cease operation altogether.
摘要翻译： 公开了一种方法和系统，以实现和控制刀片/底盘系统中的功率降低。 “最大功率降低”属性存储在刀片的VPD中（否则可以由管理实体输入或检索或计算）。 其中叶片和电源所在的机箱的管理模块使用该信息来管理当系统以超订购模式操作并且电源出现故障时叶片的功率降低。 如果需要节流，则系统知道每个刀片可用的功率减少量，并通过将系统中的刀片扩展到控制器中来控制节流，从而理想地，刀片不会完全停止运行。
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公开(公告)号：US07485809B2
公开(公告)日：2009-02-03
申请号：US11100680
申请日：2005-04-06
IPC分类号： H01R4/00
CPC分类号： G02B6/447
摘要： A system and method for implementing a cable system is disclosed. The system includes a paddle card system that includes a card, and a circuit coupled to the card and configured to couple to a server system node. The circuit indicates when the card is properly seated when the card is plugged into the server system node. As a result, errors due to the paddle card system being improperly seated are minimized.
摘要翻译： 公开了一种用于实现电缆系统的系统和方法。 该系统包括一个包括卡片的卡片系统，以及耦合到该卡并被配置为耦合到服务器系统节点的电路。 电路指示当卡插入服务器系统节点时卡正确就位。 结果是，由于卡片卡系统被错误地安置而导致的错误被最小化。
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公开(公告)号：US09054840B2
公开(公告)日：2015-06-09
申请号：US13326805
申请日：2011-12-15
CPC分类号： H04L1/0045 , H03M13/09 , H03M13/098 , H03M13/2906 , H03M13/2927 , H04L1/0061
摘要： Error detection and correction of a data transmission, including: receiving a block of data, where the block includes a predefined number of words, with each word including a parity bit, where the block of data also an error-correcting code (ECC); determining, for each word in dependence upon the parity bit of the word, whether the word of the block includes a parity error; committing each word that does not include a parity error, if only one word of the block includes a parity error: correcting the one word that includes the parity error through use of the ECC of the block and committing the corrected word.
摘要翻译： 数据传输的错误检测和校正包括：接收数据块，其中该块包括预定数量的字，其中每个字包括奇偶校验位，其中该数据块也是纠错码（ECC）; 根据单词的奇偶校验位来确定每个单词是否包括奇偶校验错误; 提交不包括奇偶校验错误的每个单词，如果块中只有一个单词包含奇偶校验错误：通过使用块的ECC并提交校正字来校正包含奇偶校验错误的一个单词。
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公开(公告)号：US20110153899A1
公开(公告)日：2011-06-23
申请号：US12644629
申请日：2009-12-22
IPC分类号： G06F13/20
CPC分类号： G06F13/385
摘要： Computer peripheral expansion apparatus, methods of operation, and computer program products including blade peripheral expansion units (‘BPEUs’), each BPEU including a peripheral interconnect multiplexer coupled for peripheral interconnect data communications through an upstream peripheral interconnect bus (‘PIB’) segment to a host blade, the upstream PIB segment fanned out by the multiplexer into two or more peripheral downstream interconnect channels, the multiplexer connecting the upstream PIB segment to only one of the downstream channels at a time; and the two or more downstream peripheral interconnect channels, at least one of the downstream channels connected to at least one peripheral interconnect device (‘PID’) in the BPEU, the peripheral interconnect device being a device that communicates with the host blade according to a peripheral interconnect data communications protocol, one of the downstream channels configured to connect to an upstream PIB segment in another BPEU.
摘要翻译： 计算机外设扩展装置，操作方法以及计算机程序产品，包括刀片外围设备扩展单元（BPEU），每个BPEU包括一个外设互连多路复用器，用于通过上游外设互连总线（“PIB”）段到外围互连数据通信 主机刀片，由多路复用器扇出的上游PIB段分成两个或更多个外围下游互连通道，多路复用器将上游PIB段一次连接到仅一条下游通道; 以及所述两个或更多个下游外围互连通道，所述下游通道中的至少一个连接到所述BPEU中的至少一个外围互连设备（“PID”），所述外围设备互连设备是根据主机刀片与所述主机刀片通信的设备 外围互连数据通信协议，其中一个下游通道被配置为连接到另一个BPEU中的上游PIB段。
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公开(公告)号：US07502991B2
公开(公告)日：2009-03-10
申请号：US11170951
申请日：2005-06-30
CPC分类号： G06F11/2007 , H04L1/0063 , H04L1/1803 , H04L1/22
摘要： A redundant communication system for providing data communication between a first computing node and a second computing node. A transmitter is provided as part of the first computing node. A receiver is provided as part of the second computing node. A first signal line carries a first data signal. The first signal line electrically couples the transmitter with the receiver. A second signal line carries a second data signal redundant to the first signal. The second signal line electrically couples the transmitter with the receiver. The receiver evaluates the first data signal to determine the presence of an error and the second node uses the second data signal if an error is detected in the first data signal.
摘要翻译： 一种用于在第一计算节点和第二计算节点之间提供数据通信的冗余通信系统。 作为第一计算节点的一部分提供发射机。 提供接收机作为第二计算节点的一部分。 第一信号线承载第一数据信号。 第一个信号线将发射器与接收器电耦合。 第二信号线将第二数据信号冗余地传送到第一信号。 第二信号线将发射器与接收器电耦合。 接收器评估第一数据信号以确定是否存在错误，并且如果在第一数据信号中检测到错误，则第二节点使用第二数据信号。
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