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公开(公告)号：US08334716B1
公开(公告)日：2012-12-18
申请号：US12580175
申请日：2009-10-15
申请人： Allan Thomas Davidson , Marwan A. Khalaf , Daniel Bowersox , Michael Menghui Zheng , Neville Carvalho
发明人： Allan Thomas Davidson , Marwan A. Khalaf , Daniel Bowersox , Michael Menghui Zheng , Neville Carvalho
IPC分类号： H03K3/00
CPC分类号： H03L7/085 , G11C7/222 , H03L7/0812
摘要： A digital phase detector circuit and corresponding monitor and control logic is presented. The digital phase detector has two storage elements, where the data input of the first storage element receives a first clock signal and the data input of the second storage element receives a second clock signal. A time shifter shifts the second clock signal by a shift period, and transmits the shifted signal to the clock input of the storage elements. The signals applied to the data inputs are transmitted from the storage elements when the clock input receives the shifted second clock signal from the time shifter. A monitor and control module samples the data output from the storage elements after each shifted second clock signal is transmitted by the time shifter. The sampling of the output data provides the data used to determine the time relationship between the first and the second clock signals.
摘要翻译： 提出了一种数字相位检测电路及相应的监控与控制逻辑。 数字相位检测器具有两个存储元件，其中第一存储元件的数据输入接收第一时钟信号，并且第二存储元件的数据输入接收第二时钟信号。 时移器将第二时钟信号移位移位周期，并将移位的信号发送到存储元件的时钟输入。 当时钟输入从时移器接收到移位的第二时钟信号时，从存储元件发送施加到数据输入端的信号。 每个移位的第二个时钟信号由时间移位器发送之后，监视器和控制模块对从存储元件输出的数据进行采样。 输出数据的采样提供用于确定第一和第二时钟信号之间的时间关系的数据。
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公开(公告)号：US20090161738A1
公开(公告)日：2009-06-25
申请号：US12283652
申请日：2008-09-15
申请人： Neville Carvalho , Allan Thomas Davidson , Andy Turudic , Bruce B. Pedersen , David W. Mendel , Kalyan Kankipati , Michael Menghui Zheng , Sergey Shumarayev , Seungmyon Park , Tim Tri Hoang , Kumara Tharmalingam
发明人： Neville Carvalho , Allan Thomas Davidson , Andy Turudic , Bruce B. Pedersen , David W. Mendel , Kalyan Kankipati , Michael Menghui Zheng , Sergey Shumarayev , Seungmyon Park , Tim Tri Hoang , Kumara Tharmalingam
CPC分类号： H04L25/14
摘要： A transceiver system with reduced latency uncertainty is described. In one implementation, the transceiver system has a word aligner latency uncertainty of zero. In another implementation, the transceiver system has a receiver-to-transmitter transfer latency uncertainty of zero. In yet another implementation, the transceiver system has a word aligner latency uncertainty of zero and a receiver-to-transmitter transfer latency uncertainty of zero. In one specific implementation, the receiver-to-transmitter transfer latency uncertainty is eliminated by using the transmitter parallel clock as a feedback signal in the transmitter phase locked loop (PLL). In one implementation, this is achieved by optionally making the transmitter divider, which generates the transmitter parallel clock, part of the feedback path of the transmitter PLL. In one implementation, the word aligner latency uncertainty is eliminated by using a bit slipper to slip bits in such a way so that the total delay due to the word alignment and bit slipping is constant for all phases of the recovered clock. This allows for having a fixed and known latency between the receipt and transmission of bits for all phases of parallelization by the deserializer. In one specific implementation, the total delay due to the bit shifting by the word aligner and the bit slipping by the bit slipper is zero since the bit slipper slips bits so as to compensate for the bit shifting that was performed by the word aligner.
摘要翻译： 描述了具有降低的等待时间不确定性的收发机系统。 在一个实现中，收发器系统具有字对齐器等待时间不确定度为零。 在另一个实现中，收发器系统具有接收器到发射器的传输等待时间不确定度为零。 在另一个实现中，收发器系统具有字对齐器延迟不确定度为零和接收器到发射器的传输等待时间不确定度为零。 在一个具体实现中，通过在发射机锁相环（PLL）中使用发射机并行时钟作为反馈信号来消除接收机到发射机的传输等待时间不确定性。 在一个实现中，这通过可选地使发射机分频器（其产生发射机并行时钟）作为发射机PLL的反馈路径的一部分来实现。 在一个实施方案中，通过使用位拖动器以这样的方式滑动位来消除字对齐器延迟不确定性，使得由于字对齐和位滑动引起的总延迟对于恢复时钟的所有阶段是恒定的。 这允许在由解串器的并行化的所有阶段的位的接收和传输之间具有固定和已知的等待时间。 在一个具体实现中，由于位对准器的位移和由位拖动器的位滑动导致的总延迟为零，因为位拖动器滑动位，以补偿由字对准器执行的位移。
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公开(公告)号：US09559881B2
公开(公告)日：2017-01-31
申请号：US12283652
申请日：2008-09-15
申请人： Neville Carvalho , Allan Thomas Davidson , Andy Turudic , Bruce B. Pedersen , David W. Mendel , Kalyan Kankipati , Michael Menghui Zheng , Sergey Shumarayev , Seungmyon Park , Tim Tri Hoang , Kumara Tharmalingam
发明人： Neville Carvalho , Allan Thomas Davidson , Andy Turudic , Bruce B. Pedersen , David W. Mendel , Kalyan Kankipati , Michael Menghui Zheng , Sergey Shumarayev , Seungmyon Park , Tim Tri Hoang , Kumara Tharmalingam
CPC分类号： H04L25/14
摘要： A transceiver system with reduced latency uncertainty is described. In one implementation, the transceiver system has a word aligner latency uncertainty of zero. In another implementation, the transceiver system has a receiver-to-transmitter transfer latency uncertainty of zero. In yet another implementation, the transceiver system has a word aligner latency uncertainty of zero and a receiver-to-transmitter transfer latency uncertainty of zero. In one specific implementation, the receiver-to-transmitter transfer latency uncertainty is eliminated by using the transmitter parallel clock as a feedback signal in the transmitter phase locked loop (PLL). In one implementation, this is achieved by optionally making the transmitter divider, which generates the transmitter parallel clock, part of the feedback path of the transmitter PLL. In one implementation, the word aligner latency uncertainty is eliminated by using a bit slipper to slip bits in such a way so that the total delay due to the word alignment and bit slipping is constant for all phases of the recovered clock. This allows for having a fixed and known latency between the receipt and transmission of bits for all phases of parallelization by the deserializer. In one specific implementation, the total delay due to the bit shifting by the word aligner and the bit slipping by the bit slipper is zero since the bit slipper slips bits so as to compensate for the bit shifting that was performed by the word aligner.
摘要翻译： 描述了具有降低的等待时间不确定性的收发机系统。 在一个实现中，收发器系统具有字对齐器等待时间不确定度为零。 在另一个实现中，收发器系统具有接收器到发射器的传输等待时间不确定度为零。 在另一个实现中，收发器系统具有字对齐器延迟不确定度为零和接收器到发射器的传输等待时间不确定度为零。 在一个具体实现中，通过在发射机锁相环（PLL）中使用发射机并行时钟作为反馈信号来消除接收机到发射机的传输等待时间不确定性。 在一个实现中，这通过可选地使发射机分频器（其产生发射机并行时钟）作为发射机PLL的反馈路径的一部分来实现。 在一个实施方案中，通过使用位拖动器以这样的方式滑动位来消除字对齐器延迟不确定性，使得由于字对齐和位滑动引起的总延迟对于恢复时钟的所有阶段是恒定的。 这允许在由解串器的并行化的所有阶段的位的接收和传输之间具有固定和已知的等待时间。 在一个具体实现中，由于位对准器的位移和由位拖动器的位滑动导致的总延迟为零，因为位拖动器滑动位，以补偿由字对准器执行的位移。
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公开(公告)号：US20120027026A1
公开(公告)日：2012-02-02
申请号：US12845672
申请日：2010-07-28
IPC分类号： H04J3/16
CPC分类号： H04J3/1682 , H04J3/04 , H04J3/0685 , H04L5/22 , H04Q2213/13208 , H04Q2213/13322
摘要： The present application discloses apparatus and methods for increasing channel utilization for a high-speed serial interface of an integrated circuit (IC). A new circuit architecture is disclosed which provides circuitry that may be programmed flexibly to support a multitude of different channel bonding schemes. In accordance with one aspect of the invention, the new architecture decouples the granularity of control-signal channel bonding from the granularity of data-aggregation channel bonding. This advantageously allows optimization of configurations for both types of channel bonding. In another aspect of the invention, the logical boundaries of bonded user channels are decoupled from the physical boundaries of the PCS modules. This decoupling advantageously eliminates a rigid constraint of previous architectures.
摘要翻译： 本申请公开了用于增加集成电路（IC）的高速串行接口的信道利用的装置和方法。 公开了一种新的电路架构，其提供可以被灵活地编程以支持多种不同的信道绑定方案的电路。 根据本发明的一个方面，新架构使控制信号信道绑定的粒度与数据聚合信道绑定的粒度分离。 这有利地允许优化用于两种类型的通道结合的配置。 在本发明的另一方面，粘合用户信道的逻辑边界与PCS模块的物理边界分离。 这种去耦有利地消除了先前架构的刚性约束。
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公开(公告)号：US08059677B1
公开(公告)日：2011-11-15
申请号：US12427960
申请日：2009-04-22
CPC分类号： G06F17/505
摘要： Structures and methods to facilitate channel bundling are disclosed. In one embodiment, signal distribution circuitry includes a data path with at least two registers coupled to adjacent sets of data channels in a bundle of data channel sets. In another embodiment, self-switch circuits allow channels in a bundle of channel-sets to switch from bundle-wide signals to locally generated signals after the bundle-wide signals have been synchronously distributed to all channel sets in the bundle. In a particular embodiment, signal distribution circuitry is used to distribute a divided clock signal. In another particular embodiment, signal distribution circuitry is used to distribute enable signals for first-in first-out circuits (“FIFOs”) located in channels of each data channel set in a channel set bundle. In a particular aspect of an embodiment, FIFO read and write operations across a channel set bundle are initiated such that a difference between read and write pointer signals is the same in each channel set.
摘要翻译： 公开了促进通道捆绑的结构和方法。 在一个实施例中，信号分配电路包括数据路径，其中至少两个寄存器耦合到一组数据信道集合中的相邻数据信道集合。 在另一个实施例中，自交换电路允许信道集合中的信道在束宽信号已经被同步分布到分组中的所有信道集之后从束范围信号切换到本地产生的信号。 在特定实施例中，信号分配电路用于分配分频时钟信号。 在另一特定实施例中，信号分配电路用于分配位于通道组束中的每个数据通道的通道中的先进先出电路（“FIFO”）的使能信号。 在一个实施例的一个特定方面，跨越信道集束的FIFO读和写操作被启动，使得每个信道集合中读指针信号和写指针信号之间的差异是相同的。
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6.发明授权Apparatus for improving power consumption of communication circuitry and associated methods 有权用于改善通信电路和相关方法的功耗的装置公开(公告)号：US09436250B1
公开(公告)日：2016-09-06
申请号：US13330635
申请日：2011-12-19
申请人： Curt Wortman , Keith Duwel , Michael Menghui Zheng
发明人： Curt Wortman , Keith Duwel , Michael Menghui Zheng
CPC分类号： H03L7/0807 , G06F1/32 , G06F1/3278 , G06F1/3296 , G06F11/0736 , G06F11/076 , G06F11/079 , H03K19/0008 , H03K19/1737 , H03K19/17728 , H03K19/1776 , H04B17/309 , Y02D10/157
摘要： An integrated circuit (IC) includes communication circuitry, a body bias generator, and a controller. The communication circuitry includes a physical medium attachment (PMA) and a physical coding sublayer (PCS). The body bias generator provides body bias signals to the PMA and PCS. The controller controls the body bias generator such that the body bias signals are controlled to improve a power consumption of the communication circuitry.
摘要翻译： 集成电路（IC）包括通信电路，体偏置发生器和控制器。 通信电路包括物理介质连接（PMA）和物理编码子层（PCS）。 身体偏置发生器向PMA和PCS提供身体偏置信号。 控制器控制身体偏置发生器，使得身体偏置信号被控制以提高通信电路的功率消耗。
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公开(公告)号：US08488623B2
公开(公告)日：2013-07-16
申请号：US12845672
申请日：2010-07-28
CPC分类号： H04J3/1682 , H04J3/04 , H04J3/0685 , H04L5/22 , H04Q2213/13208 , H04Q2213/13322
摘要： The present application discloses apparatus and methods for increasing channel utilization for a high-speed serial interface of an integrated circuit (IC). A new circuit architecture is disclosed which provides circuitry that may be programmed flexibly to support a multitude of different channel bonding schemes. In accordance with one aspect of the invention, the new architecture decouples the granularity of control-signal channel bonding from the granularity of data-aggregation channel bonding. This advantageously allows optimization of configurations for both types of channel bonding. In another aspect of the invention, the logical boundaries of bonded user channels are decoupled from the physical boundaries of the PCS modules. This decoupling advantageously eliminates a rigid constraint of previous architectures.
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8.发明授权公开(公告)号：US08188774B1
公开(公告)日：2012-05-29
申请号：US12833718
申请日：2010-07-09
申请人： Gopi Krishnamurthy , Binh Ton , Ning Xue , Tim Tri Hoang , Michael Menghui Zheng , Weiqi Ding
发明人： Gopi Krishnamurthy , Binh Ton , Ning Xue , Tim Tri Hoang , Michael Menghui Zheng , Weiqi Ding
IPC分类号： H03L7/00
CPC分类号： H03K19/1774
摘要： One embodiment relates to a method for activating an interface on an integrated circuit while a core of the integrated circuit is becoming operational. An offset calibration for a transceiver channel is performed by physical media attachment circuitry. A transmitting frequency is locked onto by a transmitter phase-locked loop for the transceiver channel, and a receiving frequency is locked onto by a receiver phase-locked loop for the transceiver channel. Subsequently, the interface is activated while a core component of the integrated circuit is becoming operational. Another embodiment pertains to an integrated circuit which includes transceiver channel circuits, an interface processor, and a reset control state machine. Another embodiment relates to control circuitry including a reset control state machine, transceiver channel circuits, a channel input steering multiplexer, and a channel output steering multiplexer. Other embodiments, aspects and features are also disclosed.
摘要翻译： 一个实施例涉及在集成电路的核心变得可操作时激活集成电路上的接口的方法。 收发器通道的偏移校准由物理介质连接电路执行。 传输频率被收发器通道的发射机锁相环锁定，并且接收频率被收发信机的接收机锁相环锁定。 随后，当集成电路的核心部件变得可操作时，该接口被激活。 另一实施例涉及包括收发信道电路，接口处理器和复位控制状态机的集成电路。 另一实施例涉及包括复位控制状态机，收发信道电路，信道输入转向多路复用器和信道输出转向多路复用器的控制电路。 还公开了其它实施例，方面和特征。
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9.发明授权CDR control architecture for robust low-latency exit from the power-saving mode of an embedded CDR in a programmable integrated circuit device 有权CDR控制架构，用于强大的低延迟退出可编程集成电路设备中嵌入式CDR的省电模式公开(公告)号：US07925913B1
公开(公告)日：2011-04-12
申请号：US11857141
申请日：2007-09-18
CPC分类号： G06F13/4295 , H04L7/0083 , H04L7/033 , H04L7/10 , Y02D10/14 , Y02D10/151
摘要： Clock data recovery (CDR) circuitry of a high-speed serial interface on a programmable integrated circuit device toggles, during the electrical idle period of the receiver of the interface, between its “lock-to-reference” (“LTR”) state and its normal “lock-to-data” (“LTD”) state. Whenever during this toggling mode the CDR circuitry toggles to the LTD state, it remains in that state for a predetermined interval and then returns to the LTR state, unless, while it is in the LTD state, it receives a signal from elsewhere in the receiver that data have been received and byte synchronization has occurred. The predetermined toggling interval preferably is long enough to obtain an LTR lock to minimize frequency drift, but short enough to avoid unnecessary delay in detection of the synchronization signal. Preferably, this interval is programmable by the user within limits determined by the characterization of the programmable device. Unreliable analog signal detection is thereby avoided.
摘要翻译： 可编程集成电路设备上的高速串行接口的时钟数据恢复（CDR）电路在接口的接收机的电空闲周期之间切换其“锁定参考”（“LTR”）状态和 其正常的“锁定数据”（“LTD”）状态。 无论何时在这个切换模式下，CDR电路切换到LTD状态，它保持在该状态一段预定的间隔，然后返回到LTR状态，除非在它处于LTD状态时，它接收来自接收器中其他地方的信号 已经接收到数据并发生字节同步。 预定的切换间隔优选地足够长以获得LTR锁定以使频率漂移最小化，但足够短以避免对同步信号的检测的不必要的延迟。 优选地，该间隔可由用户在由可编程设备的表征确定的限度内编程。 从而避免了不可靠的模拟信号检测。
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10.发明授权CDR control architecture for robust low-latency exit from the power-saving mode of an embedded CDR in a programmable integrated circuit device 有权CDR控制架构，用于强大的低延迟退出可编程集成电路设备中嵌入式CDR的省电模式公开(公告)号：US08291255B1
公开(公告)日：2012-10-16
申请号：US13082162
申请日：2011-04-07
CPC分类号： G06F13/4295 , H04L7/0083 , H04L7/033 , H04L7/10 , Y02D10/14 , Y02D10/151
摘要： Clock data recovery (CDR) circuitry of a high-speed serial interface on a programmable integrated circuit device toggles, during the electrical idle period of the receiver of the interface, between its “lock-to-reference” (“LTR”) state and its normal “lock-to-data” (“LTD”) state. Whenever during this toggling mode the CDR circuitry toggles to the LTD state, it remains in that state for a predetermined interval and then returns to the LTR state, unless, while it is in the LTD state, it receives a signal from elsewhere in the receiver that data have been received and byte synchronization has occurred. The predetermined toggling interval preferably is long enough to obtain an LTR lock to minimize frequency drift, but short enough to avoid unnecessary delay in detection of the synchronization signal. Preferably, this interval is programmable by the user within limits determined by the characterization of the programmable device. Unreliable analog signal detection is thereby avoided.
摘要翻译： 可编程集成电路设备上的高速串行接口的时钟数据恢复（CDR）电路在接口的接收机的电气空闲周期内切换其锁定参考（LTR）状态与其正常的锁定 - 数据（LTD）状态。 无论何时在这个切换模式下，CDR电路切换到LTD状态，它保持在该状态一段预定的间隔，然后返回到LTR状态，除非在它处于LTD状态时，它接收来自接收器中其他地方的信号 已经接收到数据并发生字节同步。 预定的切换间隔优选地足够长以获得LTR锁定以使频率漂移最小化，但足够短以避免对同步信号的检测的不必要的延迟。 优选地，该间隔可由用户在由可编程设备的表征确定的限度内编程。 从而避免了不可靠的模拟信号检测。
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