公开(公告)号：US09046788B2

公开(公告)日：2015-06-02

申请号：US12122929

申请日：2008-05-19

申请人： Allen H. Gabor ,  Wai-Kin Li

发明人： Allen H. Gabor ,  Wai-Kin Li

IPC分类号： G03B27/52 ,  G03B27/68 ,  G03F7/20

CPC分类号： G03F7/70333 ,  G03F7/70508 ,  G03F7/70641

摘要： A method and apparatus are provided for improving the focusing of a substrate such as a wafer during the photolithography imaging procedure of a semiconductor manufacturing process. The invention is particularly useful for step-and-scan system and the CD of two features in each exposure field are measured in fields exposed at varying focus to form at least two Bossung curves. Exposure focus instructions are calculated based on the intersection point of the curves and the wafer is then scanned and imaged based on the calculated exposure focus instructions. In another aspect of the invention, when multiple wafers are being processed operational variances may cause a drift in the focus. The focus drift can be easily corrected by measuring the critical dimension of each of the features and comparing the difference to determine if any focus offset is needed to return the focus to the original calculated focus value.

摘要翻译： 提供了一种用于在半导体制造工艺的光刻成像过程期间改善诸如晶片之类的衬底的聚焦的方法和装置。 本发明对于步进扫描系统特别有用，并且每个曝光场中的两个特征的CD在以不同焦点曝光的场中测量以形成至少两个Bossung曲线。 基于曲线的交点，然后基于计算出的曝光聚焦指令对晶片进行扫描和成像，计算曝光对焦指令。 在本发明的另一方面，当正在处理多个晶片时，操作方差可能导致焦点漂移。 可以通过测量每个特征的临界尺寸并比较差异来确定是否需要任何聚焦偏移以将焦点返回到原始计算的聚焦值，从而容易地校正聚焦漂移。

公开(公告)号：US20090284722A1

公开(公告)日：2009-11-19

申请号：US12122929

申请日：2008-05-19

申请人： Allen H. Gabor ,  Wai-Kin Li

发明人： Allen H. Gabor ,  Wai-Kin Li

IPC分类号： G03B27/42 ,  G06K9/00

CPC分类号： G03F7/70333 ,  G03F7/70508 ,  G03F7/70641

摘要： A method and apparatus are provided for improving the focusing of a substrate such as a wafer during the photolithography imaging procedure of a semiconductor manufacturing process. The invention is particularly useful for step-and-scan system and the CD of two features in each exposure field are measured in fields exposed at varying focus to form at least two Bossung curves. Exposure focus instructions are calculated based on the intersection point of the curves and the wafer is then scanned and imaged based on the calculated exposure focus instructions. In another aspect of the invention, when multiple wafers are being processed operational variances may cause a drift in the focus. The focus drift can be easily corrected by measuring the critical dimension of each of the features and comparing the difference to determine if any focus offset is needed to return the focus to the original calculated focus value.

摘要翻译： 提供了一种用于在半导体制造工艺的光刻成像过程期间改善诸如晶片之类的衬底的聚焦的方法和装置。 本发明对于步进扫描系统特别有用，并且每个曝光场中的两个特征的CD在以不同焦点曝光的场中测量以形成至少两个Bossung曲线。 基于曲线的交点，然后基于计算出的曝光聚焦指令对晶片进行扫描和成像，计算曝光对焦指令。 在本发明的另一方面，当正在处理多个晶片时，操作方差可能导致焦点漂移。 可以通过测量每个特征的临界尺寸并比较差异来确定是否需要任何聚焦偏移以将焦点返回到原始计算的聚焦值，从而容易地校正聚焦漂移。

公开(公告)号：US08507346B2

公开(公告)日：2013-08-13

申请号：US12949148

申请日：2010-11-18

申请人： Martin Burkhardt ,  Matthew E. Colburn ,  Allen H. Gabor ,  Oleg Gluschenkov ,  Scott D. Halle ,  Howard S. Landis ,  Helen Wang

发明人： Martin Burkhardt ,  Matthew E. Colburn ,  Allen H. Gabor ,  Oleg Gluschenkov ,  Scott D. Halle ,  Howard S. Landis ,  Helen Wang

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/84 ,  H01L21/338 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/311 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L29/78 ,  H01L21/28123 ,  H01L21/32139 ,  H01L22/12 ,  H01L22/26

摘要： A method of forming a semiconductor device having a substrate, an active region and an inactive region includes: forming a hardmask layer over the substrate; transferring a first pattern into the hardmask layer in the active region of the semiconductor device; forming one or more fills in the inactive region; forming a cut-away hole within, covering, or partially covering, the one or more fills to expose a portion of the hardmask layer, the exposed portion being within the one or more fills; and exposing the hardmask layer to an etchant to divide the first pattern into a second pattern including at least two separate elements.

摘要翻译： 一种形成具有衬底，有源区和非活性区的半导体器件的方法包括：在衬底上形成硬掩模层; 将第一图案转移到半导体器件的有源区中的硬掩模层中; 在非活性区域中形成一个或多个填充物; 在所述一个或多个填充物内部，覆盖或部分地覆盖所述硬掩模层的一部分以暴露所述硬掩模层的一部分内的切除孔，所述暴露部分在所述一个或多个填充物内; 以及将所述硬掩模层暴露于蚀刻剂以将所述第一图案划分成包括至少两个分离元件的第二图案。

公开(公告)号：US08455162B2

公开(公告)日：2013-06-04

申请号：US13170316

申请日：2011-06-28

申请人： Allen H. Gabor ,  Vinayan C. Menon

发明人： Allen H. Gabor ,  Vinayan C. Menon

IPC分类号： G03F9/00

CPC分类号： G03F1/42 ,  G03F1/70 ,  G03F9/7076 ,  G03F9/708

摘要： A plurality of reticles for printing structures in the same lithography level includes an alignment structure pattern within a same relative location in each reticle. Each set of process segmentations in a grating has a reticle segmentation pitch, which is common across all gratings in the plurality of reticles. Within each pair of alignment structure patterns that occupy the same relative location in any two of the plurality of reticles, the process segmentations in one reticle are shifted relative to the process segmentations in the other reticle by a fraction of a reticle segmentation pitch. After printing all patterns in the plurality of reticles, a composite printed process segmentation structure on the substrate includes printed segmentation structures that are spaced by 1/n times the printed segmentation pitch. The pattern for the next level can be aligned to the composite printed process segmentation structure in a single alignment operation.

摘要翻译： 用于在相同光刻级别打印结构的多个掩模版包括在每个掩模版中的相同相对位置内的对准结构图案。 光栅中的每组处理分段具有掩模版分割间距，其在多个光栅中的所有光栅上是共同的。 在每对对准结构图案对中，在多个光罩中的任何两个中占据相同的相对位置，一个掩模版中的处理分割相对于另一个掩模版中的处理分段移位一定的标线片分割间距。 在印刷多个掩模版中的所有图案之后，基板上的复合印刷工艺分割结构包括间隔开印刷分割间距的1 / n倍的印刷分割结构。 可以在单个对齐操作中将下一级别的模式与复合打印过程分段结构对齐。

公开(公告)号：US08361683B2

公开(公告)日：2013-01-29

申请号：US12757344

申请日：2010-04-09

申请人： Christopher P. Ausschnitt ,  Allen H. Gabor ,  Nelson M. Felix

发明人： Christopher P. Ausschnitt ,  Allen H. Gabor ,  Nelson M. Felix

IPC分类号： G03F9/00 ,  G01B11/00

CPC分类号： H01L23/544 ,  G03F7/70633 ,  H01L2924/0002 ,  H01L2924/00

摘要： A wafer includes an active region and a kerf region surrounding at least a portion of the active region. The wafer also includes a target region having a rectangular shape with a width and a length greater than the width, the target region including one or more target patterns, at least one of the target patterns being formed by two sub-patterns disposed at opposing corners of a target rectangle disposable within the target region.

摘要翻译： 晶片包括活性区域和围绕有源区域的至少一部分的切口区域。 晶片还包括具有宽度和长度大于宽度的矩形形状的目标区域，目标区域包括一个或多个目标图案，目标图案中的至少一个由设置在相对角部处的两个子图案形成 在目标区域内可放置的目标矩形。

公开(公告)号：US20110248388A1

公开(公告)日：2011-10-13

申请号：US12757344

申请日：2010-04-09

申请人： Christopher P. Ausschnitt ,  Allen H. Gabor ,  Nelson M. Felix

发明人： Christopher P. Ausschnitt ,  Allen H. Gabor ,  Nelson M. Felix

IPC分类号： H01L23/544 ,  G03F7/20

CPC分类号： H01L23/544 ,  G03F7/70633 ,  H01L2924/0002 ,  H01L2924/00

摘要： A wafer includes an active region and a kerf region surrounding at least a portion of the active region. The wafer also includes a target region having a rectangular shape with a width and a length greater than the width, the target region including one or more target patterns, at least one of the target patterns being formed by two sub-patterns disposed at opposing corners of a target rectangle disposable within the target region.

摘要翻译： 晶片包括有源区域和围绕有源区域的至少一部分的切口区域。 晶片还包括具有宽度和长度大于宽度的矩形形状的目标区域，目标区域包括一个或多个目标图案，目标图案中的至少一个由设置在相对角部处的两个子图案形成 在目标区域内可放置的目标矩形。

公开(公告)号：US07993815B2

公开(公告)日：2011-08-09

申请号：US11853353

申请日：2007-09-11

申请人： Matthew E. Colburn ,  Allen H. Gabor ,  Scott D. Halle ,  Donald J. Samuels

发明人： Matthew E. Colburn ,  Allen H. Gabor ,  Scott D. Halle ,  Donald J. Samuels

IPC分类号： H01L21/8229

CPC分类号： G11C11/412 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/115

摘要： Methods of forming line ends and a related memory cell including the line ends are disclosed. In one embodiment, the method includes forming a first device element and a second device element separated from the first device element by a space; and forming a first line extending from the first device element, the first line including a bulbous line end over the space and distanced from the first device element, and a second line extending from the second device element, the second line including a bulbous line end over the space and distanced from the second device element.

摘要翻译： 公开了形成线端的方法和包括线端的相关存储单元。 在一个实施例中，该方法包括通过空间形成与第一器件元件分离的第一器件元件和第二器件元件; 以及形成从所述第一装置元件延伸的第一线，所述第一线包括在所述空间上并与所述第一装置元件间隔开的球形线端，以及从所述第二装置元件延伸的第二线，所述第二线包括球根线端 并且与第二设备元件分开。

公开(公告)号：US20090181330A1

公开(公告)日：2009-07-16

申请号：US12013627

申请日：2008-01-14

申请人： Allen H. Gabor ,  Scott D. Halle ,  Helen Wang

发明人： Allen H. Gabor ,  Scott D. Halle ,  Helen Wang

IPC分类号： G03F7/20

CPC分类号： H01L21/0337 ,  G03F7/70433 ,  G03F7/70466

摘要： An underlayer to be patterned with a composite pattern is formed on a substrate. The composite pattern is decomposed into a first pattern and a second pattern, each having reduced complexity than the composite pattern. A hard mask layer is formed directly on the underlying layer. A first photoresist is applied over the hard mask layer and lithographically patterned with the first pattern, which is transferred into the hard mask layer by a first etch. A second photoresist is applied over the hard mask layer. The second photoresist is patterned with the second pattern to expose portions of the underlying layer. The exposed portions of the underlying layer are etched employing the second photoresist and the hard mask layer, which contains the first pattern so that the composite pattern is transferred into the underlying layer.

摘要翻译： 在基板上形成图案化复合图案的底层。 复合图案被分解为第一图案和第二图案，每个图案具有比复合图案更低的复杂度。 硬掩模层直接形成在下层上。 将第一光致抗蚀剂施加在硬掩模层上并用第一图案进行光刻图案化，其通过第一蚀刻转移到硬掩模层中。 在硬掩模层上施加第二光致抗蚀剂。 用第二图案对第二光致抗蚀剂进行图案化以暴露下层的部分。 使用包含第一图案的第二光致抗蚀剂和硬掩模层来蚀刻下层的暴露部分，使得复合图案被转移到下层中。

公开(公告)号：US20080246097A1

公开(公告)日：2008-10-09

申请号：US12117014

申请日：2008-05-08

申请人： Brent Alan Anderson ,  Shahid Ahmad Butt ,  Allen H. Gabor ,  Patrick Edward Lindo ,  Edward Joseph Nowak ,  Jed Hickory Rankin

发明人： Brent Alan Anderson ,  Shahid Ahmad Butt ,  Allen H. Gabor ,  Patrick Edward Lindo ,  Edward Joseph Nowak ,  Jed Hickory Rankin

IPC分类号： H01L27/088

CPC分类号： H01L22/20

摘要： A method of reducing parametric variation in an integrated circuit (IC) chip and an IC chip with reduced parametric variation. The method includes: on a first wafer having a first arrangement of chips, each IC chip divided into a second arrangement of regions, measuring a test device parameter of test devices distributed in different regions; and on a second wafer having the first arrangement of IC chips and the second arrangement of regions, adjusting a functional device parameter of identically designed field effect transistors within one or more regions of all IC chips of the second wafer based on a values of the test device parameter measured on test devices in regions of the IC chip of the first wafer by a non-uniform adjustment of physical or metallurgical polysilicon gate widths of the identically designed field effect transistors from region to region within each IC chip.

摘要翻译： 一种降低参数变化减小的集成电路（IC）芯片和IC芯片的参数变化的方法。 该方法包括：在具有第一芯片布置的第一晶片上，将每个IC芯片分成第二区域布置，测量分布在不同区域中的测试装置的测试装置参数; 并且在具有IC芯片的第一布置和第二区域布置的第二晶片上，基于测试值调整第二晶片的所有IC芯片的一个或多个区域内相同设计的场效应晶体管的功能器件参数 在第一晶片的IC芯片的区域中的测试装置上测量的器件参数通过在每个IC芯片内的区域到区域的相同设计的场效应晶体管的物理或冶金多晶硅栅极宽度的不均匀调整而不均匀地调整。

公开(公告)号：US20080154420A1

公开(公告)日：2008-06-26

申请号：US11613238

申请日：2006-12-20

申请人： Colin J. Brodsky ,  Michael M. Crouse ,  Allen H. Gabor

发明人： Colin J. Brodsky ,  Michael M. Crouse ,  Allen H. Gabor

IPC分类号： G06F19/00

CPC分类号： G05B19/41875 ,  G03F7/70508 ,  G03F7/70558 ,  G03F7/70625 ,  G03F7/70875 ,  G05B2219/32182 ,  G05B2219/32187 ,  G05B2219/32188 ,  G05B2219/37224 ,  G05B2219/45028 ,  H01L22/12 ,  H01L22/20

摘要： A method of controlling one or more critical dimension (CD) features, dependent upon at least a first and a second processing parameter, with a single metrology step, while still enabling decoupled feedback to the first and the second processing parameter, includes an initial process characterization; producing a production piece; a single metrology step to determine the critical dimensions of the produced features; solving a system of equations simultaneously for individual feedback correction values for the first and second processing parameters; and applying the individual feedback correction values to their respective processing parameters.

摘要翻译： 一种基于至少第一和第二处理参数的单个度量步骤来控制一个或多个关键维度（CD）特征的方法，同时仍然使能到第一和第二处理参数的解耦反馈，包括初始过程 表征 生产一块; 一个单一的度量步骤来确定所产生的特征的关键尺寸; 针对第一和第二处理参数的各个反馈校正值同时求解方程组; 以及将各个反馈校正值应用于它们各自的处理参数。