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公开(公告)号：US08990515B2
公开(公告)日：2015-03-24
申请号：US13160373
申请日：2011-06-14
CPC分类号： G06F8/51 , G06F9/44536
摘要： The present invention extends to methods, systems, and computer program products for aliasing buffers. Embodiment of the inventions supporting buffer aliasing through introduction of a level of indirection between a source program's buffer accesses and the target executable physical buffers, and binding the logical buffer accesses to actual physical buffer accesses at runtime. A variety of techniques for can be used supporting runtime aliasing of buffers, in a system which otherwise disallows such runtime aliasing between separately defined buffers in the target executable code. Binding of logical buffer accesses in the source program to the actual physical buffers defined in the target executable code is delayed until runtime.
摘要翻译： 本发明扩展到用于混叠缓冲器的方法，系统和计算机程序产品。 本发明的实施例通过引入源程序的缓冲器访问和目标可执行物理缓冲器之间的间接级别来支持缓冲器混叠，并且在运行时将逻辑缓冲器访问绑定到实际物理缓冲器访问。 可以使用各种技术来支持缓冲器的运行时混叠，在系统中，否则不允许在目标可执行代码中的单独定义的缓冲区之间的这种运行时混叠。 将源程序中的逻辑缓冲区访问绑定到目标可执行代码中定义的实际物理缓冲区将被延迟到运行时。
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公开(公告)号：US08677322B2
公开(公告)日：2014-03-18
申请号：US13172521
申请日：2011-06-29
IPC分类号： G06F9/44
CPC分类号： G06F8/41 , G06F11/3624
摘要： The present invention extends to methods, systems, and computer program products for debugging in a multiple address space environment. Embodiments of the invention include techniques for recording debug information used for translating between an abstract unified address space and multiple address spaces at a target system (e.g., a co-processor, such as, a GPU or other accelerator). A table is stored in the recorded debug information. The table includes one or more entries mapping compiler assigned IDs to address spaces. During debugging within a symbolic debugger, the recorded debug information can be used for viewing program data across multiple address spaces in a live debugging session.
摘要翻译： 本发明扩展到用于在多地址空间环境中进行调试的方法，系统和计算机程序产品。 本发明的实施例包括用于记录用于在抽象统一地址空间和目标系统（例如协同处理器，例如GPU或其他加速器）处的多个地址空间之间进行翻译的调试信息的技术。 表中存储有记录的调试信息。 该表包括将编译器分配的ID映射到地址空间的一个或多个条目。 在符号调试器调试期间，记录的调试信息可用于在实时调试会话中跨多个地址空间查看程序数据。
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公开(公告)号：US20130007712A1
公开(公告)日：2013-01-03
申请号：US13172521
申请日：2011-06-29
IPC分类号： G06F9/44
CPC分类号： G06F8/41 , G06F11/3624
摘要： The present invention extends to methods, systems, and computer program products for debugging in a multiple address space environment. Embodiments of the invention include techniques for recording debug information used for translating between an abstract unified address space and multiple address spaces at a target system (e.g., a co-processor, such as, a GPU or other accelerator). A table is stored in the recorded debug information. The table includes one or more entries mapping compiler assigned IDs to address spaces. During debugging within a symbolic debugger, the recorded debug information can be used for viewing program data across multiple address spaces in a live debugging session.
摘要翻译： 本发明扩展到用于在多地址空间环境中进行调试的方法，系统和计算机程序产品。 本发明的实施例包括用于记录用于在抽象统一地址空间和目标系统（例如协同处理器，例如GPU或其他加速器）处的多个地址空间之间进行翻译的调试信息的技术。 表中存储有记录的调试信息。 该表包括将编译器分配的ID映射到地址空间的一个或多个条目。 在符号调试器调试期间，记录的调试信息可用于在实时调试会话中跨多个地址空间查看程序数据。
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公开(公告)号：US20120317558A1
公开(公告)日：2012-12-13
申请号：US13158226
申请日：2011-06-10
IPC分类号： G06F9/45
CPC分类号： G06F9/44521 , G06F8/443 , G06F9/44542 , G06F9/4552
摘要： The present invention extends to methods, systems, and computer program products for binding executable code at runtime. Embodiments of the invention include late binding of specified aspects of code to improve execution performance. A runtime dynamically binds lower level code based on runtime information to optimize execution of a higher level algorithm. Aspects of a higher level algorithm having a requisite (e.g., higher) impact on execution performance can be targeted for late binding. Improved performance can be achieved with minimal runtime costs using late binding for aspects having the requisite execution performance impact.
摘要翻译： 本发明扩展到用于在运行时绑定可执行代码的方法，系统和计算机程序产品。 本发明的实施例包括代码的特定方面的后期绑定以改善执行性能。 运行时基于运行时信息动态地绑定较低级别的代码，以优化较高级算法的执行。 具有对执行性能的必要（例如更高）影响的较高级算法的方面可以针对后期绑定。 通过对具有必要的执行性能影响的方面的后期绑定，可以以最小的运行时成本实现改进的性能。
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公开(公告)号：US20120317556A1
公开(公告)日：2012-12-13
申请号：US13158966
申请日：2011-06-13
IPC分类号： G06F9/45
CPC分类号： G06F8/451
摘要： The present invention extends to methods, systems, and computer program products for optimizing execution of kernels. Embodiments of the invention include an optimization framework for optimizing runtime execution of kernels. During compilation, information about the execution properties of a kernel are identified and stored alongside the executable code for the kernel. At runtime, calling contexts access the information. The calling contexts interpret the information and optimize kernel execution based on the interpretation.
摘要翻译： 本发明扩展到用于优化内核的执行的方法，系统和计算机程序产品。 本发明的实施例包括用于优化内核的运行时执行的优化框架。 在编译期间，内核的执行属性的信息被识别并存储在内核的可执行代码旁边。 在运行时，调用上下文访问信息。 调用上下文根据解释来解释信息并优化内核执行。
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公开(公告)号：US08533698B2
公开(公告)日：2013-09-10
申请号：US13158966
申请日：2011-06-13
IPC分类号： G06F9/44
CPC分类号： G06F8/451
摘要： The present invention extends to methods, systems, and computer program products for optimizing execution of kernels. Embodiments of the invention include an optimization framework for optimizing runtime execution of kernels. During compilation, information about the execution properties of a kernel are identified and stored alongside the executable code for the kernel. At runtime, calling contexts access the information. The calling contexts interpret the information and optimize kernel execution based on the interpretation.
摘要翻译： 本发明扩展到用于优化内核的执行的方法，系统和计算机程序产品。 本发明的实施例包括用于优化内核的运行时执行的优化框架。 在编译期间，内核的执行属性的信息被识别并存储在内核的可执行代码旁边。 在运行时，调用上下文访问信息。 调用上下文根据解释来解释信息并优化内核执行。
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公开(公告)号：US08468507B2
公开(公告)日：2013-06-18
申请号：US13158226
申请日：2011-06-10
IPC分类号： G06F9/45
CPC分类号： G06F9/44521 , G06F8/443 , G06F9/44542 , G06F9/4552
摘要： The present invention extends to methods, systems, and computer program products for binding executable code at runtime. Embodiments of the invention include late binding of specified aspects of code to improve execution performance. A runtime dynamically binds lower level code based on runtime information to optimize execution of a higher level algorithm. Aspects of a higher level algorithm having a requisite (e.g., higher) impact on execution performance can be targeted for late binding. Improved performance can be achieved with minimal runtime costs using late binding for aspects having the requisite execution performance impact.
摘要翻译： 本发明扩展到用于在运行时绑定可执行代码的方法，系统和计算机程序产品。 本发明的实施例包括代码的特定方面的后期绑定以改善执行性能。 运行时基于运行时信息动态地绑定较低级别的代码，以优化较高级算法的执行。 具有对执行性能的必要（例如更高）影响的较高级算法的方面可以针对后期绑定。 通过对具有必要的执行性能影响的方面的后期绑定，可以以最小的运行时成本实现改进的性能。
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公开(公告)号：US20120324430A1
公开(公告)日：2012-12-20
申请号：US13160373
申请日：2011-06-14
IPC分类号： G06F9/45
CPC分类号： G06F8/51 , G06F9/44536
摘要： The present invention extends to methods, systems, and computer program products for aliasing buffers. Embodiment of the inventions supporting buffer aliasing through introduction of a level of indirection between a source program's buffer accesses and the target executable physical buffers, and binding the logical buffer accesses to actual physical buffer accesses at runtime. A variety of techniques for can be used supporting runtime aliasing of buffers, in a system which otherwise disallows such runtime aliasing between separately defined buffers in the target executable code. Binding of logical buffer accesses in the source program to the actual physical buffers defined in the target executable code is delayed until runtime.
摘要翻译： 本发明扩展到用于混叠缓冲器的方法，系统和计算机程序产品。 本发明的实施例通过引入源程序的缓冲器访问和目标可执行物理缓冲器之间的间接级别来支持缓冲器混叠，并且在运行时将逻辑缓冲器访问绑定到实际物理缓冲器访问。 可以使用各种技术来支持缓冲器的运行时混叠，在系统中，否则不允许在目标可执行代码中的单独定义的缓冲区之间的这种运行时混叠。 将源程序中的逻辑缓冲区访问绑定到目标可执行代码中定义的实际物理缓冲区将被延迟到运行时。
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9.发明授权公开(公告)号：US08589867B2
公开(公告)日：2013-11-19
申请号：US12819108
申请日：2010-06-18
IPC分类号： G06F9/44
CPC分类号： G06F8/45
摘要： Described herein are techniques for generating invocation stubs for a data parallel programming model so that a data parallel program written in a statically-compiled high-level programming language may be more declarative, reusable, and portable than traditional approaches. With some of the described techniques, invocation stubs are generated by a compiler and those stubs bridge a logical arrangement of data parallel computations to the actual physical arrangement of a target data parallel hardware for that data parallel computation.
摘要翻译： 这里描述的是用于生成用于数据并行编程模型的调用存根的技术，使得以静态编译的高级编程语言编写的数据并行程序可以比传统方法更具声明性，可重复使用和便携式。 利用一些所描述的技术，调用存根由编译器生成，并且这些存根将数据并行计算的逻辑排列与用于该数据并行计算的目标数据并行硬件的实际物理排列相结合。
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公开(公告)号：US08539458B2
公开(公告)日：2013-09-17
申请号：US13158077
申请日：2011-06-10
申请人： Weirong Zhu , Yosseff Levanoni
发明人： Weirong Zhu , Yosseff Levanoni
CPC分类号： G06F8/44
摘要： The present invention extends to methods, systems, and computer program products for changing addressing mode during code generation. Generally, embodiments of the invention use a compiler transformation to transform lower level code from one address alignment to another address alignment. The transformation can be based upon assumptions of a source programming language. Based on the assumptions, the transformation can eliminate arithmetic operations that compensate for different addressing alignment, resulting in more efficient code. Some particular embodiments use a compiler transformation to transform an Intermediate Representation (“IR”) from one-byte addressing alignment into multi-byte (e.g., four-byte) addressing alignment.
摘要翻译： 本发明扩展到用于在代码生成期间改变寻址模式的方法，系统和计算机程序产品。 通常，本发明的实施例使用编译器转换来将较低级别的代码从一个地址对齐转换到另一个地址对齐。 转换可以基于源程序设计语言的假设。 基于这些假设，转换可以消除补偿不同寻址对齐的算术运算，从而产生更有效的代码。 一些特定实施例使用编译器变换将中间表示（“IR”）从一字节寻址对准转换为多字节（例如，四字节）寻址对齐。
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