公开(公告)号：US08372750B2

公开(公告)日：2013-02-12

申请号：US12890100

申请日：2010-09-24

申请人： Amitabh Jain ,  Peijun Chen ,  Jorge A. Kittl

发明人： Amitabh Jain ,  Peijun Chen ,  Jorge A. Kittl

IPC分类号： H01L21/44

CPC分类号： H01L21/28518 ,  H01L21/823807 ,  H01L21/823835 ,  H01L29/665 ,  H01L29/78

摘要： According to one embodiment of the invention, a method for nickel silicidation includes providing a substrate having a source region, a gate region, and a drain region, forming a source in the source region and a drain in the drain region, annealing the source and the drain, implanting, after the annealing the source and the drain, a heavy ion in the source region and the drain region, depositing a nickel layer in each of the source and drain regions, and heating the substrate to form a nickel silicide region in each of the source and drain regions by heating the substrate.

摘要翻译： 根据本发明的一个实施例，一种用于镍硅化的方法包括提供具有源极区，栅极区和漏极区的衬底，在源区中形成源极和在漏极区中形成漏极，退火源和 漏极，在源极和漏极退火之后注入源区域和漏极区域中的重离子，在源极和漏极区域中的每一个中沉积镍层，并加热衬底以形成硅化镍区域 每个源极和漏极区域通过加热衬底。

公开(公告)号：US07825025B2

公开(公告)日：2010-11-02

申请号：US10959674

申请日：2004-10-04

申请人： Amitabh Jain ,  Peijun Chen ,  Jorge A. Kittl

发明人： Amitabh Jain ,  Peijun Chen ,  Jorge A. Kittl

IPC分类号： H01L21/44 ,  H01L21/477

CPC分类号： H01L21/28518 ,  H01L21/823807 ,  H01L21/823835 ,  H01L29/665 ,  H01L29/78

摘要： According to one embodiment of the invention, a method for nickel silicidation includes providing a substrate having a source region, a gate region, and a drain region, forming a source in the source region and a drain in the drain region, annealing the source and the drain, implanting, after the annealing the source and the drain, a heavy ion in the source region and the drain region, depositing a nickel layer in each of the source and drain regions, and heating the substrate to form a nickel silicide region in each of the source and drain regions by heating the substrate.

摘要翻译： 根据本发明的一个实施例，一种用于镍硅化的方法包括提供具有源极区，栅极区和漏极区的衬底，在源区中形成源极和在漏极区中形成漏极，退火源和 漏极，在源极和漏极退火之后注入源区域和漏极区域中的重离子，在源极和漏极区域中的每一个中沉积镍层，并加热衬底以形成硅化镍区域 每个源极和漏极区域通过加热衬底。

公开(公告)号：US20060073656A1

公开(公告)日：2006-04-06

申请号：US10959674

申请日：2004-10-04

申请人： Amitabh Jain ,  Peijun Chen ,  Jorge Kittl

发明人： Amitabh Jain ,  Peijun Chen ,  Jorge Kittl

IPC分类号： H01L21/8238 ,  H01L21/44

CPC分类号： H01L21/28518 ,  H01L21/823807 ,  H01L21/823835 ,  H01L29/665 ,  H01L29/78

摘要： According to one embodiment of the invention, a method for nickel silicidation includes providing a substrate having a source region, a gate region, and a drain region, forming a source in the source region and a drain in the drain region, annealing the source and the drain, implanting, after the annealing the source and the drain, a heavy ion in the source region and the drain region, depositing a nickel layer in each of the source and drain regions, and heating the substrate to form a nickel silicide region in each of the source and drain regions by heating the substrate.

公开(公告)号：US20070049022A1

公开(公告)日：2007-03-01

申请号：US11551374

申请日：2006-10-20

申请人： Peijun Chen ,  Duofeng Yue ,  Amitabh Jain ,  Sue Crank ,  Thomas Bonifield ,  Homi Mogul

发明人： Peijun Chen ,  Duofeng Yue ,  Amitabh Jain ,  Sue Crank ,  Thomas Bonifield ,  Homi Mogul

IPC分类号： H01L21/44

CPC分类号： H01L21/28518 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： The invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a gate structure located over a substrate, the gate structure including a gate dielectric layer and gate electrode layer. The semiconductor device may further include source/drain regions located in/over the substrate and adjacent the gate structure, and a nickel alloy silicide located in the source/drain regions, the nickel alloy silicide having an amount of indium located therein.

摘要翻译： 本发明提供一种半导体器件，一种制造方法以及一种用于制造包括该半导体器件的集成电路的方法。 除了其他元件之外，半导体器件可以包括位于衬底上的栅极结构，栅极结构包括栅极电介质层和栅极电极层。 该半导体器件还可以包括位于衬底中或栅极结构附近的源极/漏极区域和位于源极/漏极区域中的镍合金硅化物，所述镍合金硅化物具有位于其中的铟的量。

公开(公告)号：US20070141840A1

公开(公告)日：2007-06-21

申请号：US11678950

申请日：2007-02-26

申请人： Peijun Chen ,  Duofeng Yue ,  Amitabh Jain ,  Sue Crank ,  Thomas Bonifield ,  Homi Mogul

发明人： Peijun Chen ,  Duofeng Yue ,  Amitabh Jain ,  Sue Crank ,  Thomas Bonifield ,  Homi Mogul

IPC分类号： H01L21/44

CPC分类号： H01L21/28518 ,  H01L21/26586 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： The present invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a substrate (110), as well as a nickel silicide region (170) located over the substrate (110), the nickel silicide region (170) having an amount of indium located therein.

摘要翻译： 本发明提供一种半导体装置及其制造方法以及包括该半导体装置的集成电路的制造方法。 除了其它元件之外，半导体器件可以包括衬底（110）以及位于衬底（110）上方的硅化镍区域（170），所述硅化镍区域（170）具有位于其中的铟的量。

公开(公告)号：US20060223295A1

公开(公告)日：2006-10-05

申请号：US11096660

申请日：2005-04-01

申请人： Peijun Chen ,  Duofeng Yue ,  Amitabh Jain ,  Sue Crank ,  Thomas Bonifield ,  Homi Mogul

发明人： Peijun Chen ,  Duofeng Yue ,  Amitabh Jain ,  Sue Crank ,  Thomas Bonifield ,  Homi Mogul

IPC分类号： H01L21/4763

CPC分类号： H01L21/28518 ,  H01L21/26586 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： The present invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a substrate (110), as well as a nickel silicide region (170) located over the substrate (110), the nickel silicide region (170) having an amount of indium located therein.

摘要翻译： 本发明提供一种半导体装置及其制造方法以及包括该半导体装置的集成电路的制造方法。 除了其它元件之外，半导体器件可以包括衬底（110）以及位于衬底（110）上方的硅化镍区域（170），所述硅化镍区域（170）具有位于其中的铟的量。

公开(公告)号：US6143634A

公开(公告)日：2000-11-07

申请号：US123828

申请日：1998-07-28

申请人： Robert M. Wallace ,  Peijun Chen

发明人： Robert M. Wallace ,  Peijun Chen

IPC分类号： H01L21/28 ,  H01L21/30 ,  H01L21/768 ,  H01L21/3205

CPC分类号： H01L21/76814 ,  H01L21/28176 ,  H01L21/28518 ,  H01L21/3003 ,  H01L21/76826 ,  H01L21/76843 ,  H01L21/76864 ,  H01L21/76879

摘要： Channel-hot-carrier reliability can be improved by deuterium passivation of the gate interface. By performing high temperature steps (above 300 degrees Celsius) in a deuterium-containing ambient, harmful depletion of deuterium due to diffusion away from the gate interface is avoided.

摘要翻译： 通过栅极接口的氘钝化可以提高通道 - 热载体的可靠性。 通过在含氘环境中进行高温步骤（高于300摄氏度），避免了由于扩散离开栅极界面而导致的氘的有害耗尽。

公开(公告)号：US20060035463A1

公开(公告)日：2006-02-16

申请号：US10914928

申请日：2004-08-10

申请人： Sue Crank ,  Shirin Siddiqui ,  Deborah Riley ,  Trace Hurd ,  Peijun Chen

发明人： Sue Crank ,  Shirin Siddiqui ,  Deborah Riley ,  Trace Hurd ,  Peijun Chen

IPC分类号： H01L21/4763

CPC分类号： H01L21/28518 ,  H01L21/76829

摘要： A method of preparing a die comprises treating exposed silicon to form an oxide prior to silicide formation; and depositing metal on the oxide. The metal may comprise titanium, cobalt, nickel, platinum, palladium, tungsten, molybdenum, or combinations thereof on the oxide. The oxide may be less than or equal to about 15 angstroms thick. In various embodiments, treating exposed silicon to form an oxide comprises forming a non- thermal oxide. Treating exposed silicon to form an oxide may also comprise treating the exposed silicon with an oxidizing plasma; alternatively, treating exposed silicon to form an oxide may comprise forming a chemical oxide. In certain other embodiments, treating exposed silicon to form an oxide comprises treating exposed silicon with a solution comprising ammonium hydroxide, hydrogen peroxide, and water; hydrochloric acid, hydrogen peroxide, and water; hydrogen peroxide; ozone; ozonated deionized water; or combinations thereof.

摘要翻译： 制备模具的方法包括在硅化物形成之前处理暴露的硅以形成氧化物; 并在氧化物上沉积金属。 金属可以在氧化物上包含钛，钴，镍，铂，钯，钨，钼或它们的组合。 氧化物可以小于或等于约15埃厚。 在各种实施方案中，处理暴露的硅以形成氧化物包括形成非热氧化物。 处理暴露的硅以形成氧化物还可以包括用氧化等离子体处理暴露的硅; 或者，处理暴露的硅以形成氧化物可包括形成化学氧化物。 在某些其他实施方案中，处理暴露的硅以形成氧化物包括用包含氢氧化铵，过氧化氢和水的溶液处理暴露的硅; 盐酸，过氧化氢和水; 过氧化氢; 臭氧; 臭氧化去离子水; 或其组合。

公开(公告)号：US20050269651A1

公开(公告)日：2005-12-08

申请号：US11138746

申请日：2005-05-25

申请人： Peijun Chen ,  Tsai Wilman ,  Mathieu Caymax ,  Jan Maes

发明人： Peijun Chen ,  Tsai Wilman ,  Mathieu Caymax ,  Jan Maes

IPC分类号： C23C16/02 ,  C23C16/30 ,  C23C16/34 ,  C23C16/40 ,  C23C16/44 ,  C23C16/455 ,  C23C16/56 ,  H01L21/28 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L21/471 ,  H01L29/51 ,  H01L29/772

CPC分类号： H01L21/28194 ,  C23C16/0218 ,  C23C16/308 ,  C23C16/345 ,  C23C16/405 ,  C23C16/45525 ,  C23C16/45529 ,  C23C16/45531 ,  C23C16/45536 ,  C23C16/56 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/3141 ,  H01L21/3144 ,  H01L21/31604 ,  H01L21/31645 ,  H01L21/318 ,  H01L21/3185 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a method for fabricating a dielectric stack in an integrated circuit comprising the steps of (i) forming a high-k dielectric layer on a semiconductor substrate, (ii) subjecting the semiconductor substrate with the high-k dielectric layer to a nitrogen comprising vapor phase reactant and silicon comprising vapor phase reactant in a plasma-enhanced chemical vapor deposition process (PECVD) or a plasma-enhanced atomic layer chemical vapor deposition (PE ALCVD) process. Furthermore, the present invention provides a dielectric stack in an integrated circuit comprising (i) a high-k dielectric layer comprising at least a high-k material, (ii) a dielectric layer comprising at least silicon and nitrogen; (iii) an intermediate layer disposed between the high-k dielectric layer and the dielectric layer, the intermediate layer comprising the high-k material, silicon, and nitrogen.

摘要翻译： 本发明提供了一种用于在集成电路中制造电介质叠层的方法，包括以下步骤：（i）在半导体衬底上形成高k电介质层，（ii）使具有高k电介质层的半导体衬底经受 包含气相反应物的氮和包含气相反应物的硅在等离子体增强化学气相沉积工艺（PECVD）或等离子体增强原子层化学气相沉积（PE ALCVD）工艺中。 此外，本发明提供了一种集成电路中的电介质堆叠，包括（i）至少包含高k材料的高k电介质层，（ii）至少包含硅和氮的电介质层; （iii）设置在高k电介质层和电介质层之间的中间层，中间层包含高k材料，硅和氮。

公开(公告)号：US20060024938A1

公开(公告)日：2006-02-02

申请号：US10901697

申请日：2004-07-29

申请人： Duofeng Yue ,  Peijun Chen ,  Jiong-Ping Lu ,  Thomas Bonifield ,  Noel Russell

发明人： Duofeng Yue ,  Peijun Chen ,  Jiong-Ping Lu ,  Thomas Bonifield ,  Noel Russell

IPC分类号： H01L21/336 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/6656 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6653

摘要： The present invention provides a method for manufacturing a semiconductor device, and a method for manufacturing an integrated circuit including the semiconductor device, and a semiconductor device. The method for manufacturing a semiconductor device, among other steps, includes forming source/drain regions (290) in a substrate (210), the source/drain regions (290) located proximate a gate structure having sidewall spacers (270) and positioned over the substrate (210), and modifying a footprint of the sidewall spacers (270) by forming protective regions (410) proximate a base of the sidewall spacers (270). The method further includes forming metal silicide regions (610) in the source/drain regions (290).

摘要翻译： 本发明提供一种半导体器件的制造方法以及包括该半导体器件的集成电路的制造方法以及半导体器件。 除了其他步骤之外，制造半导体器件的方法包括在衬底（210）中形成源极/漏极区域（290），源/漏极区域（290）位于具有侧壁间隔物（270）的栅极结构附近并定位在 衬底（210），并且通过在侧壁间隔物（270）的基部附近形成保护区（410）来修改侧壁间隔物（270）的覆盖区。 该方法还包括在源/漏区（290）中形成金属硅化物区（610）。