公开(公告)号：US08798570B2

公开(公告)日：2014-08-05

申请号：US13323103

申请日：2011-12-12

申请人： Amr M. Fahim ,  Stephen A. Jantzi ,  Afshin Mellati

发明人： Amr M. Fahim ,  Stephen A. Jantzi ,  Afshin Mellati

IPC分类号： H04B1/16 ,  H03H11/12 ,  H03H11/46

CPC分类号： H03G3/3052 ,  H04B1/1027

摘要： A receiver, such as a television tuner, includes a radio frequency (RF) filter circuit. The RF filter circuit includes a filter, a first node, and a second node coupled to the filter, and a conversion signal path having an input coupled to the first node and an output coupled to the second node, the conversion signal path having an active mixer coupled between the first node and the second node. The active mixer can include, for example, a first transconductor and a first mixer coupled in series between the first node and the second node. The RF filter circuit further includes a feedback signal path having an input coupled to the second node and an output coupled to the first node, the feedback signal path including a second transconductor and a second mixer coupled in series between the second node and the first node.

摘要翻译： 诸如电视调谐器的接收机包括射频（RF）滤波器电路。 RF滤波器电路包括滤波器，第一节点和耦合到滤波器的第二节点，以及具有耦合到第一节点的输入和耦合到第二节点的输出的转换信号路径，转换信号路径具有活动 耦合在第一节点和第二节点之间的混合器。 有源混频器可以包括例如串联耦合在第一节点和第二节点之间的第一跨导器和第一混频器。 RF滤波器电路还包括具有耦合到第二节点的输入和耦合到第一节点的输出的反馈信号路径，反馈信号路径包括串联耦合在第二节点和第一节点之间的第二跨导器和第二混频器 。

公开(公告)号：US20130149983A1

公开(公告)日：2013-06-13

申请号：US13323103

申请日：2011-12-12

申请人： Amr M. Fahim ,  Stephen A. Jantzi ,  Afshin Mellati

发明人： Amr M. Fahim ,  Stephen A. Jantzi ,  Afshin Mellati

IPC分类号： H04B1/26

CPC分类号： H03G3/3052 ,  H04B1/1027

摘要： A receiver, such as a television tuner, includes a radio frequency (RF) filter circuit. The RF filter circuit includes a filter, a first node, and a second node coupled to the filter, and a conversion signal path having an input coupled to the first node and an output coupled to the second node, the conversion signal path having an active mixer coupled between the first node and the second node. The active mixer can include, for example, a first transconductor and a first mixer coupled in series between the first node and the second node. The RF filter circuit further includes a feedback signal path having an input coupled to the second node and an output coupled to the first node, the feedback signal path including a second transconductor and a second mixer coupled in series between the second node and the first node.

摘要翻译： 诸如电视调谐器的接收机包括射频（RF）滤波器电路。 RF滤波器电路包括滤波器，第一节点和耦合到滤波器的第二节点，以及具有耦合到第一节点的输入和耦合到第二节点的输出的转换信号路径，转换信号路径具有活动 耦合在第一节点和第二节点之间的混合器。 有源混频器可以包括例如串联耦合在第一节点和第二节点之间的第一跨导器和第一混频器。 RF滤波器电路还包括具有耦合到第二节点的输入和耦合到第一节点的输出的反馈信号路径，反馈信号路径包括串联耦合在第二节点和第一节点之间的第二跨导器和第二混频器 。

公开(公告)号：US08666352B2

公开(公告)日：2014-03-04

申请号：US13327836

申请日：2011-12-16

申请人： Stephen A. Jantzi ,  Amr M. Fahim

发明人： Stephen A. Jantzi ,  Amr M. Fahim

IPC分类号： H04B1/26

CPC分类号： H04B1/3805 ,  H04B1/525

摘要： A radio frequency (RF) receiver, such as a television tuner, includes a harmonic cancellation circuit. The harmonic cancellation circuit includes a primary signal path to generate a first intermediate frequency (IF) signal by mixing an RF signal with a reference signal and a harmonic feedforward signal path to generate a second IF signal representing signal content of the RF signal near an nth-order harmonic of a frequency fLO of the first reference signal, n comprising a positive integer. The harmonic cancellation circuit further includes a summation stage to generate a third IF signal based on a difference between the first IF signal and the second IF signal.

摘要翻译： 诸如电视调谐器的射频（RF）接收机包括谐波消除电路。 谐波消除电路包括通过将RF信号与参考信号和谐波前馈信号路径混合来产生第一中频（IF）信号的主信号路径，以产生表示在第n个附近的RF信号的信号内容的第二IF信号 第一参考信号的频率fLO的顺序谐波，n包括正整数。 谐波消除电路还包括基于第一IF信号和第二IF信号之间的差产生第三IF信号的求和级。

公开(公告)号：US20130157604A1

公开(公告)日：2013-06-20

申请号：US13327836

申请日：2011-12-16

申请人： Stephen A. Jantzi ,  Amr M. Fahim

发明人： Stephen A. Jantzi ,  Amr M. Fahim

IPC分类号： H04B1/10

CPC分类号： H04B1/3805 ,  H04B1/525

摘要： A radio frequency (RF) receiver, such as a television tuner, includes a harmonic cancellation circuit. The harmonic cancellation circuit includes a primary signal path to generate a first intermediate frequency (IF) signal by mixing an RF signal with a reference signal and a harmonic feedforward signal path to generate a second IF signal representing signal content of the RF signal near an nth-order harmonic of a frequency fLO of the first reference signal, n comprising a positive integer. The harmonic cancellation circuit further includes a summation stage to generate a third IF signal based on a difference between the first IF signal and the second IF signal.

摘要翻译： 诸如电视调谐器的射频（RF）接收机包括谐波消除电路。 谐波消除电路包括通过将RF信号与参考信号和谐波前馈信号路径混合来产生第一中频（IF）信号的主信号路径，以产生表示在第n个附近的RF信号的信号内容的第二IF信号 第一参考信号的频率fLO的顺序谐波，n包括正整数。 谐波消除电路还包括基于第一IF信号和第二IF信号之间的差产生第三IF信号的求和级。

公开(公告)号：US07034610B2

公开(公告)日：2006-04-25

申请号：US10861379

申请日：2004-06-07

申请人： Stephen A. Jantzi ,  Anilkumar V. Tammineedi ,  Jungwoo Song ,  Lawrence M. Burns ,  Donald G. McMullin ,  Agnes N. Woo

发明人： Stephen A. Jantzi ,  Anilkumar V. Tammineedi ,  Jungwoo Song ,  Lawrence M. Burns ,  Donald G. McMullin ,  Agnes N. Woo

IPC分类号： H03F1/14

CPC分类号： H03G3/001 ,  H03G1/0088

摘要： An upstream amplifier is integrated on a substrate with a digital-to-analog converter (DAC) to form an integrated circuit. In an embodiment, a low-pass filter is also integrated on the substrate. The output signal level of the upstream amplifier is controllable. In embodiments, fine adjustments are made to the output signal level of the upstream amplifier by varying a bias current of the DAC. A software control bit is used to switch between a power-on mode of operation and a power-down mode of operation. The upstream amplifier transmits in a burst mode. The power consumption of the upstream amplifier scales with the amplifier's output signal level. A high degree of matching is attained between the positive and negative paths of the upstream amplifier. This provides high immunity from common-mode disturbances such as substrate noise, clock spurs, and glitches caused by a gain change.

摘要翻译： 上游放大器集成在具有数模转换器（DAC）的基板上，以形成集成电路。 在一个实施例中，低通滤波器也集成在基板上。 上游放大器的输出信号电平是可控的。 在实施例中，通过改变DAC的偏置电流对上游放大器的输出信号电平进行微调。 软件控制位用于在上电操作模式和掉电操作模式之间切换。 上游放大器以突发模式发送。 上游放大器的功耗随放大器的输出信号电平而变化。 在上游放大器的正和负路径之间达到高度的匹配。 这提供了诸如衬底噪声，时钟刺激和由增益变化引起的毛刺等共模干扰的高抗扰性。

公开(公告)号：US20120086592A1

公开(公告)日：2012-04-12

申请号：US13226233

申请日：2011-09-06

申请人： Stephen A. Jantzi ,  Anilkumar V. Tammineedi ,  Jungwoo Song ,  Lawrence M. Burns ,  Donald G. McMullin ,  Anges N. Woo

发明人： Stephen A. Jantzi ,  Anilkumar V. Tammineedi ,  Jungwoo Song ,  Lawrence M. Burns ,  Donald G. McMullin ,  Anges N. Woo

IPC分类号： H03M1/66

CPC分类号： H03G3/001 ,  H03G1/0088

摘要： An upstream amplifier is integrated on a substrate with a digital-to-analog converter (DAC) to form an integrated circuit. In an embodiment, a low-pass filter is also integrated on the substrate. The output signal level of the upstream amplifier is controllable. In embodiments, fine adjustments are made to the output signal level of the upstream amplifier by varying a bias current of the DAC. A software control bit is used to switch between a power-on mode of operation and a power-down mode of operation. The upstream amplifier transmits in a burst mode. The power consumption of the upstream amplifier scales with the amplifier's output signal level. A high degree of matching is attained between the positive and negative paths of the upstream amplifier. This provides high immunity from common-mode disturbances such as substrate noise, clock spurs, and glitches caused by a gain change.

摘要翻译： 上游放大器集成在具有数模转换器（DAC）的基板上，以形成集成电路。 在一个实施例中，低通滤波器也集成在基板上。 上游放大器的输出信号电平是可控的。 在实施例中，通过改变DAC的偏置电流对上游放大器的输出信号电平进行微调。 软件控制位用于在上电操作模式和掉电操作模式之间切换。 上游放大器以突发模式发送。 上游放大器的功耗随放大器的输出信号电平而变化。 在上游放大器的正和负路径之间达到高度的匹配。 这提供了诸如衬底噪声，时钟刺激和由增益变化引起的毛刺等共模干扰的高抗扰性。

公开(公告)号：US07636007B2

公开(公告)日：2009-12-22

申请号：US10937982

申请日：2004-09-10

申请人： Myles Wakayama ,  Stephen A. Jantzi ,  Kwang Young Kim ,  Yee Ling “Felix” Cheung ,  Ka Wai Tong

发明人： Myles Wakayama ,  Stephen A. Jantzi ,  Kwang Young Kim ,  Yee Ling “Felix” Cheung ,  Ka Wai Tong

IPC分类号： H03K17/00

CPC分类号： H03L7/0996 ,  H03L7/0891 ,  H03L7/183

摘要： A low jitter, high phase resolution phase lock loop incorporating a ring oscillator-type VCO is designed and constructed to operate at a characteristic frequency M times higher than a required output clock frequency. Multi-phase output signals are taken from the VCO and selected through a Gray code MUX, prior to being divided down to the output clock frequency by a divide-by-M frequency divider circuit. Operating the VCO at frequencies in excess of the output clock frequency, allows jitter to be averaged across a timing cycle M and further allows a reduction in the number of output phase taps, by a scale factor M, without reducing the phase resolution or granularity of the output signal.

摘要翻译： 包含环形振荡器型VCO的低抖动，高相位分辨率锁相环被设计和构造成以比要求的输出时钟频率M倍高的特征频率工作。 在通过M分频电路将其分频到输出时钟频率之前，通过格雷码MUX从VCO中取出多相输出信号。 在超过输出时钟频率的频率下操作VCO允许在定时周期M之间平均抖动，并且进一步允许减小比例因子M的输出相位抽头的数量，而不会降低相位分辨率或粒度 输出信号。

公开(公告)号：US06747510B2

公开(公告)日：2004-06-08

申请号：US10163143

申请日：2002-06-07

申请人： Stephen A. Jantzi ,  Anilkumar V. Tammineedi ,  Jungwoo Song ,  Lawrence M. Burns ,  Donald G. McMullin ,  Agnes N. Woo

发明人： Stephen A. Jantzi ,  Anilkumar V. Tammineedi ,  Jungwoo Song ,  Lawrence M. Burns ,  Donald G. McMullin ,  Agnes N. Woo

IPC分类号： H03F152

CPC分类号： H03G3/001 ,  H03G1/0088

摘要： An upstream amplifier is integrated on a substrate with a digital-to-analog converter (DAC) to form an integrated circuit. In an embodiment, a low-pass filter is also integrated on the substrate. The output signal level of the upstream amplifier is controllable. In embodiments, fine adjustments are made to the output signal level of the upstream amplifier by varying a bias current of the DAC. A software control bit is used to switch between a power-on mode of operation and a power-down mode of operation. The upstream amplifier transmits in a burst mode. The power consumption of the upstream amplifier scales with the amplifier's output signal level. A high degree of matching is attained between the positive and negative paths of the upstream amplifier. This provides high immunity from common-mode disturbances such as substrate noise, clock spurs, and glitches caused by a gain change.

摘要翻译： 上游放大器集成在具有数模转换器（DAC）的基板上，以形成集成电路。 在一个实施例中，低通滤波器也集成在基板上。 上游放大器的输出信号电平是可控的。 在实施例中，通过改变DAC的偏置电流对上游放大器的输出信号电平进行微调。 软件控制位用于在上电操作模式和掉电操作模式之间切换。 上游放大器以突发模式发送。 上游放大器的功耗随放大器的输出信号电平而变化。 在上游放大器的正和负路径之间达到高度的匹配。 这提供了诸如衬底噪声，时钟刺激和由增益变化引起的毛刺等共模干扰的高抗扰性。

公开(公告)号：US08334721B2

公开(公告)日：2012-12-18

申请号：US13226233

申请日：2011-09-06

申请人： Stephen A. Jantzi ,  Anilkumar V. Tammineedi ,  Jungwoo Song ,  Lawrence M. Burns ,  Donald G. McMullin ,  Agnes N. Woo

发明人： Stephen A. Jantzi ,  Anilkumar V. Tammineedi ,  Jungwoo Song ,  Lawrence M. Burns ,  Donald G. McMullin ,  Agnes N. Woo

IPC分类号： H03F1/14

CPC分类号： H03G3/001 ,  H03G1/0088

摘要： An upstream amplifier is integrated on a substrate with a digital-to-analog converter (DAC) to form an integrated circuit. In an embodiment, a low-pass filter is also integrated on the substrate. The output signal level of the upstream amplifier is controllable. In embodiments, fine adjustments are made to the output signal level of the upstream amplifier by varying a bias current of the DAC. A software control bit is used to switch between a power-on mode of operation and a power-down mode of operation. The upstream amplifier transmits in a burst mode. The power consumption of the upstream amplifier scales with the amplifier's output signal level. A high degree of matching is attained between the positive and negative paths of the upstream amplifier. This provides high immunity from common-mode disturbances such as substrate noise, clock spurs, and glitches caused by a gain change.

摘要翻译： 上游放大器集成在具有数模转换器（DAC）的基板上，以形成集成电路。 在一个实施例中，低通滤波器也集成在基板上。 上游放大器的输出信号电平是可控的。 在实施例中，通过改变DAC的偏置电流对上游放大器的输出信号电平进行微调。 软件控制位用于在上电操作模式和掉电操作模式之间切换。 上游放大器以突发模式发送。 上游放大器的功耗随放大器的输出信号电平而变化。 在上游放大器的正和负路径之间达到高度的匹配。 这提供了诸如衬底噪声，时钟刺激和由增益变化引起的毛刺等共模干扰的高抗扰性。

公开(公告)号：US06791379B1

公开(公告)日：2004-09-14

申请号：US09456230

申请日：1999-12-07

申请人： Myles Wakayama ,  Stephen A. Jantzi ,  Kwang Young Kim ,  Yee Ling Felix Cheung ,  Ka Wai Tong

发明人： Myles Wakayama ,  Stephen A. Jantzi ,  Kwang Young Kim ,  Yee Ling Felix Cheung ,  Ka Wai Tong

IPC分类号： H03L706

CPC分类号： H03L7/0996 ,  H03L7/0891 ,  H03L7/183

摘要： A low jitter, high phase resolution phase lock loop incorporating a ring oscillator-type VCO is designed and constructed to operate at a characteristic frequency M times higher than a required output clock frequency. Multi-phase output signals are taken from the VCO and selected through a Gray code MUX, prior to being divided down to the output clock frequency by a divide-by-M frequency divider circuit. Operating the VCO at frequencies in excess of the output clock frequency, allows jitter to be averaged across a timing cycle M and further allows a reduction in the number of output phase taps, by a scale factor M, without reducing the phase resolution or granularity of the output signal.

摘要翻译： 包含环形振荡器型VCO的低抖动，高相位分辨率锁相环被设计和构造成以比要求的输出时钟频率M倍高的特征频率工作。 在通过M分频电路将其分频到输出时钟频率之前，通过格雷码MUX从VCO中取出多相输出信号。 在超过输出时钟频率的频率下操作VCO允许在定时周期M之间平均抖动，并且进一步允许减小比例因子M的输出相位抽头的数量，而不会降低相位分辨率或粒度 输出信号。