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    STRESS ISOLATION FEATURES FOR STACKED DIES
    1.
    发明申请
    STRESS ISOLATION FEATURES FOR STACKED DIES 审中-公开
    应力分离特征用于堆积的模具

    公开(公告)号：US20170022051A1

    公开(公告)日：2017-01-26

    申请号：US15092234

    申请日：2016-04-06

    Applicant: ANALOG DEVICES, INC.

    Inventor： Xiaojie Xue ,  Michael J. Zylinski ,  Thomas M. Goida ,  Kathleen O. O'Donnell

    IPC: B81B7/00 ,  B81C1/00 ,  H01L23/24 ,  H01L25/065

    CPC classification number: B81B7/0048 ,  B81B2207/115 ,  B81C1/00365 ,  B81C2201/0147 ,  B81C2203/0136 ,  H01L23/057 ,  H01L23/562 ,  H01L25/0657 ,  H01L2225/06575

    Abstract: An integrated device package is disclosed. The package can include a carrier, such as first integrated device die, and a second integrated device die stacked on the first integrated device die. The package can include a buffer layer which coats at least a portion of an exterior surface of the first integrated device die and which is disposed between the second integrated device die and the first integrated device die. The buffer layer can comprise a pattern to reduce transmission of stresses between the first integrated device die and the second integrated device die.

    Abstract translation: 公开了一种集成器件封装。 封装可以包括诸如第一集成器件管芯的载体和堆叠在第一集成器件管芯上的第二集成器件管芯。 封装可以包括缓冲层，该缓冲层涂覆第一集成器件管芯的外表面的至少一部分，并且设置在第二集成器件管芯和第一集成器件管芯之间。 缓冲层可以包括用于减少第一集成器件管芯和第二集成器件裸片之间的应力传输的图案。

    Vertical mount package and wafer level packaging therefor
    5.
    发明授权
    Vertical mount package and wafer level packaging therefor 有权
    垂直安装封装和晶圆级封装

    公开(公告)号：US09278851B2

    公开(公告)日：2016-03-08

    申请号：US14484151

    申请日：2014-09-11

    Applicant: ANALOG DEVICES, INC.

    Inventor： Xiaojie Xue

    IPC: H01L23/48 ,  B81B7/00 ,  H01L21/50 ,  H01L23/04 ,  H01L23/498 ,  H01L25/065 ,  B81C1/00 ,  H01L23/00

    CPC classification number: B81B7/0077 ,  B81B2201/0242 ,  B81B2201/025 ,  B81B2207/095 ,  B81B2207/096 ,  B81C1/00325 ,  B81C1/00333 ,  B81C1/00873 ,  B81C2203/0118 ,  H01L21/50 ,  H01L23/041 ,  H01L23/49805 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2224/85 ,  H01L2224/81

    Abstract: Vertical mount packages and methods for making the same are disclosed. A method for manufacturing a vertical mount package includes providing a device substrate with a plurality of device regions on a front surface, and a plurality of through-wafer vias. MEMS devices or integrated circuits are formed or mounted onto the device regions. A capping substrate having recesses is mounted over the device substrate, enclosing the device regions within cavities defined by the recesses. A plurality of aligned through-wafer contacts extend through the capping substrate and the device substrate. The device substrate and capping substrate can be singulated by cutting through the aligned through-wafer contacts, with the severed through-wafer contacts forming vertical mount leads. A vertical mount package includes a device sealed between a device substrate and a capping substrate. At least of the side edges of the package includes exposed conductive elements for vertical mount leads.

    Abstract translation: 公开了垂直安装封装及其制造方法。 一种用于制造垂直安装封装的方法包括：在前表面上提供具有多个器件区域的器件基板，以及多个贯通晶片通孔。 MEMS器件或集成电路形成或安装到器件区域上。 具有凹槽的封盖基板安装在器件基板上，将器件区域包围在由凹槽限定的空腔内。 多个对准的跨晶片触点延伸穿过封盖衬底和器件衬底。 可以通过切割对准的通过晶片的触点来切割器件衬底和封盖衬底，切断的晶片接触件形成垂直安装引线。 垂直安装封装包括密封在器件基板和封盖基板之间的器件。 封装的至少侧边缘包括用于垂直安装引线的露出的导电元件。

    DOUBLE-SIDED PACKAGE
    6.
    发明申请
    DOUBLE-SIDED PACKAGE 有权
    双面包

    公开(公告)号：US20140217566A1

    公开(公告)日：2014-08-07

    申请号：US13757299

    申请日：2013-02-01

    Applicant: ANALOG DEVICES, INC.

    Inventor： Thomas M. Goida ,  Xiaojie Xue

    IPC: H01L23/495 ,  H01L23/00

    CPC classification number: H01L23/49575 ,  G01P1/023 ,  H01L23/04 ,  H01L23/10 ,  H01L23/3107 ,  H01L24/03 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/00

    Abstract: Various embodiments of an integrated device package are disclosed herein. The package may include a leadframe having a first side and a second side opposite the first side. The leadframe can include a plurality of leads surrounding a die mounting region. A first package lid may be mounted on the first side of the leadframe to form a first cavity, and a first integrated device die may be mounted on the first side of the leadframe within the first cavity. A second integrated device die can be mounted on the second side of the leadframe. At least one lead of the plurality of leads can provide electrical communication between the first integrated device die and the second integrated device die.

    Abstract translation: 本文公开了集成器件封装的各种实施例。 封装可以包括具有第一侧和与第一侧相对的第二侧的引线框架。 引线框架可以包括围绕模具安装区域的多个引线。 第一封装盖可以安装在引线框架的第一侧上以形成第一腔，并且第一集成器件裸片可以安装在第一腔内的引线框架的第一侧上。 第二集成器件管芯可以安装在引线框架的第二侧上。 多个引线中的至少一个引线可以在第一集成器件管芯和第二集成器件管芯之间提供电连通。

    Double-sided package
    8.
    发明授权
    Double-sided package 有权
    双面包装

    公开(公告)号：US09209121B2

    公开(公告)日：2015-12-08

    申请号：US13757299

    申请日：2013-02-01

    Applicant: Analog Devices, Inc.

    Inventor： Thomas M. Goida ,  Xiaojie Xue

    IPC: H01L23/495 ,  H01L23/04 ,  H01L23/00 ,  G01P1/02

    CPC classification number: H01L23/49575 ,  G01P1/023 ,  H01L23/04 ,  H01L23/10 ,  H01L23/3107 ,  H01L24/03 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/00

    Abstract: Various embodiments of an integrated device package are disclosed herein. The package may include a leadframe having a first side and a second side opposite the first side. The leadframe can include a plurality of leads surrounding a die mounting region. A first package lid may be mounted on the first side of the leadframe to form a first cavity, and a first integrated device die may be mounted on the first side of the leadframe within the first cavity. A second integrated device die can be mounted on the second side of the leadframe. At least one lead of the plurality of leads can provide electrical communication between the first integrated device die and the second integrated device die.

    Abstract translation: 本文公开了集成器件封装的各种实施例。 封装可以包括具有第一侧和与第一侧相对的第二侧的引线框架。 引线框架可以包括围绕模具安装区域的多个引线。 第一封装盖可以安装在引线框架的第一侧上以形成第一腔，并且第一集成器件裸片可以安装在第一腔内的引线框架的第一侧上。 第二集成器件管芯可以安装在引线框架的第二侧上。 多个引线中的至少一个引线可以在第一集成器件管芯和第二集成器件管芯之间提供电连通。

    INTEGRATED DEVICE DIE AND PACKAGE WITH STRESS REDUCTION FEATURES
    9.
    发明申请
    INTEGRATED DEVICE DIE AND PACKAGE WITH STRESS REDUCTION FEATURES 有权
    集成设备和包装与应力减少特性

    公开(公告)号：US20150181697A1

    公开(公告)日：2015-06-25

    申请号：US14577128

    申请日：2014-12-19

    Applicant: ANALOG DEVICES, INC.

    Inventor： Thomas M. Goida ,  Xiaojie Xue

    IPC: H05K1/02 ,  H05K1/18 ,  H01L21/78

    CPC classification number: H01L25/0657 ,  B81B7/0048 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/562 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/10158 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599

    Abstract: An integrated device die and package is disclosed. The integrated device die includes a unitary body. The unitary body can have an upper portion comprising one or more active components. The upper portion can have first and second opposing lateral sides defining at least a portion of a periphery of the upper portion such that an upper surface of the upper portion is disposed between upper edges of the first and second opposing lateral sides. The unitary body can also have a lower portion monolithically formed with the upper portion. The lower portion can comprise a pedestal extending downwardly from the upper portion. The pedestal can be laterally inset from lower edges of the first and second opposing lateral sides. The pedestal can include a distal end portion configured to couple to a carrier.

    Abstract translation: 公开了一种集成器件管芯和封装。 集成器件裸片包括一体式。 整体可以具有包括一个或多个活性组分的上部部分。 上部可以具有限定上部的周边的至少一部分的第一和第二相对侧边，使得上部的上表面设置在第一和第二相对的侧面的上边缘之间。 整体也可以具有与上部一体地形成的下部。 下部可以包括从上部向下延伸的基座。 基座可以从第一和第二相对侧面的下边缘侧向插入。 基座可以包括配置成联接到托架的远端部分。

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