公开(公告)号：US20130200471A1

公开(公告)日：2013-08-08

申请号：US13364976

申请日：2012-02-02

申请人： André P. Labonté ,  Richard S. Wise

发明人： André P. Labonté ,  Richard S. Wise

IPC分类号： H01L29/78 ,  H01L21/768

CPC分类号： H01L21/28247 ,  H01L21/76814 ,  H01L21/76888 ,  H01L21/76897 ,  H01L29/66545

摘要： An alignment tolerant electrical contact is formed by providing a substrate on which is a first electrically conductive region (e.g., a MOSFET gate) having an upper surface, the first electrically conductive region being laterally bounded by a first dielectric region, applying a mask having an opening extending partly over a contact region (e.g., for the MOSFET source or drain) on the substrate and over a part of the upper surface, forming a passage through the first dielectric region extending to the contact region and the part of the upper surface, thereby exposing the contact region and the part of the upper surface, converting the part of the upper surface to a second dielectric region and filling the opening with a conductor making electrical contact with the contact region but electrically insulated from the electrically conductive region by the second dielectric region.

摘要翻译： 通过提供其上具有上表面的第一导电区域（例如，MOSFET栅极）的衬底来形成对准容限的电接触，所述第一导电区域被第一介电区域横向界定，施加具有 部分地覆盖在衬底上并在上表面的一部分上的接触区域（例如，用于MOSFET源极或漏极）上的开口，形成通过延伸到接触区域和上表面的部分的第一介电区域的通道， 从而暴露接触区域和上表面的一部分，将上表面的一部分转换成第二电介质区域，并且用与接触区域电接触但与导电区域电绝缘的导体填充开口 电介质区域。

公开(公告)号：US08580628B2

公开(公告)日：2013-11-12

申请号：US13365030

申请日：2012-02-02

申请人： André P. Labonté ,  Richard S. Wise ,  Ying Li ,  Brett H. Engel

发明人： André P. Labonté ,  Richard S. Wise ,  Ying Li ,  Brett H. Engel

IPC分类号： H01L21/336

CPC分类号： H01L21/76897 ,  H01L21/76834 ,  H01L21/823828 ,  H01L21/823871 ,  H01L29/66545

摘要： An integrated circuit having a mis-alignment tolerant electrical contact is formed by providing a semiconductor containing substrate over which is a first FET gate laterally bounded by a first dielectric region, replacing an upper portion of the first FET gate with a second dielectric region, applying a mask having an opening extending partly over an adjacent source or drain contact region of the substrate and over a part of the second dielectric region above the first FET gate, forming an opening through the first dielectric region extending to the contact region and the part of the second dielectric region, and filling the opening with a conductor making electrical connection with the contact region but electrically insulated from the first FET gate by the second dielectric region. A further FET gate may also be provided having an electrical contact thereto formed separately from the source-drain contact.

摘要翻译： 具有不对准容限的电接触的集成电路是通过提供半导体衬底形成的，其上是由第一介电区横向界定的第一FET栅极，用第二电介质区域代替第一FET栅极的上部，施加 掩模，其具有部分地在所述衬底的相邻源极或漏极接触区域上方延伸的开口以及在所述第一FET栅极上方的所述第二电介质区域的一部分上方，形成穿过延伸到所述接触区域的所述第一电介质区域的开口， 第二电介质区域，并且用与该接触区域电连接但与第一FET栅极与第二电介质区域电绝缘的导体填充该开口。 还可以提供另外的FET栅极，其具有与源极 - 漏极触点分开形成的电接触。

公开(公告)号：US20130200441A1

公开(公告)日：2013-08-08

申请号：US13365030

申请日：2012-02-02

申请人： André P. Labonté ,  Richard S. Wise ,  Ying Li ,  Brett H. Engel

发明人： André P. Labonté ,  Richard S. Wise ,  Ying Li ,  Brett H. Engel

IPC分类号： H01L29/78 ,  H01L21/768

CPC分类号： H01L21/76897 ,  H01L21/76834 ,  H01L21/823828 ,  H01L21/823871 ,  H01L29/66545

摘要： An integrated circuit having a mis-alignment tolerant electrical contact is formed by providing a semiconductor containing substrate over which is a first FET gate laterally bounded by a first dielectric region, replacing an upper portion of the first FET gate with a second dielectric region, applying a mask having an opening extending partly over an adjacent source or drain contact region of the substrate and over a part of the second dielectric region above the first FET gate, forming an opening through the first dielectric region extending to the contact region and the part of the second dielectric region, and filling the opening with a conductor making electrical connection with the contact region but electrically insulated from the first FET gate by the second dielectric region. A further FET gate may also be provided having an electrical contact thereto formed separately from the source-drain contact.

摘要翻译： 具有不对准容限的电接触的集成电路是通过提供半导体衬底形成的，其上是由第一介电区横向界定的第一FET栅极，用第二电介质区域代替第一FET栅极的上部，施加 掩模，其具有部分地在所述衬底的相邻源极或漏极接触区域上方延伸的开口以及在所述第一FET栅极上方的所述第二电介质区域的一部分上方，形成穿过延伸到所述接触区域的所述第一电介质区域的开口， 第二电介质区域，并且用与该接触区域电连接但与第一FET栅极与第二电介质区域电绝缘的导体填充该开口。 还可以提供另外的FET栅极，其具有与源极 - 漏极触点分开形成的电接触。

公开(公告)号：US08507375B1

公开(公告)日：2013-08-13

申请号：US13364976

申请日：2012-02-02

申请人： André P. Labonté ,  Richard S. Wise

发明人： André P. Labonté ,  Richard S. Wise

IPC分类号： H01L21/44

CPC分类号： H01L21/28247 ,  H01L21/76814 ,  H01L21/76888 ,  H01L21/76897 ,  H01L29/66545

摘要： An alignment tolerant electrical contact is formed by providing a substrate on which is a first electrically conductive region (e.g., a MOSFET gate) having an upper surface, the first electrically conductive region being laterally bounded by a first dielectric region, applying a mask having an opening extending partly over a contact region (e.g., for the MOSFET source or drain) on the substrate and over a part of the upper surface, forming a passage through the first dielectric region extending to the contact region and the part of the upper surface, thereby exposing the contact region and the part of the upper surface, converting the part of the upper surface to a second dielectric region and filling the opening with a conductor making electrical contact with the contact region but electrically insulated from the electrically conductive region by the second dielectric region.

摘要翻译： 通过提供其上具有上表面的第一导电区域（例如，MOSFET栅极）的衬底来形成对准容限的电接触，所述第一导电区域被第一介电区域横向界定，施加具有 部分地覆盖在衬底上并在上表面的一部分上的接触区域（例如，用于MOSFET源极或漏极）上的开口，形成通过延伸到接触区域和上表面的部分的第一介电区域的通道， 从而暴露接触区域和上表面的一部分，将上表面的一部分转换成第二电介质区域，并且用与接触区域电接触但与导电区域电绝缘的导体填充开口 电介质区域。