公开(公告)号：US5053648A

公开(公告)日：1991-10-01

申请号：US521764

申请日：1990-05-10

申请人： Andreas A. J. M. van den Elshout ,  Hendrikus J. M. Veendrick ,  Dirk W. Harberts

发明人： Andreas A. J. M. van den Elshout ,  Hendrikus J. M. Veendrick ,  Dirk W. Harberts

IPC分类号： G11C17/18 ,  G11C11/00 ,  G11C11/40

CPC分类号： G11C11/005

摘要： A master slice semiconductor integrated circuit comprising ROM memory cells which consist of NMOS-transistors as well as PMOS-transistors. In order to increase the integration density on the master slice, the NMOS-transistors and the PMOS-transistors (memory cells) in one and the same row are controlled via one and the same word line. The circuit includes row selection means, for example, an exclusive-OR circuit for each row, for selecting either a single row of NMOS cells or a single row of PMOS cells.

公开(公告)号：US5250823A

公开(公告)日：1993-10-05

申请号：US804468

申请日：1991-12-05

申请人： Hendrikus J. M. Veendrick ,  Andreas A. J. M. van den Elshout ,  Dirk W. Harberts

发明人： Hendrikus J. M. Veendrick ,  Andreas A. J. M. van den Elshout ,  Dirk W. Harberts

IPC分类号： H01L27/118 ,  H01L27/104 ,  H01L29/76

CPC分类号： H01L27/11807

摘要： A gate array circuit includes a row of consecutively arranged n-channel transistors and an adjacent row of p-channel transistors. Both rows are composed of at least three subrows with two subrows of narrow transistors and one subrow of wide transistors, of which the channel width is at least three times the width of the narrow transistors. The gate electrodes are common to the three subrows. Preferably, the wide subrow is arranged centrally between the narrow subrows. This construction affords the advantage of a very high density and a very high flexibility in designing the functions to be realized.

摘要翻译： 门阵列电路包括连续布置的n沟道晶体管和相邻的p沟道晶体管行。 两行由至少三个具有两个子晶体的窄晶体管和一个宽晶体管的子线组成，其中沟道宽度至少为窄晶体管宽度的三倍。 栅电极对于三个子线是共同的。 优选地，宽的子行布置在狭窄的子宫之间的中心。 这种结构在设计要实现的功能方面具有非常高的密度和非常高的灵活性的优点。