利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

27 条记录 (耗时 0.032 秒)

    Method and computer program for generating grounded shielding wires for signal wiring
    2.
    发明授权
    Method and computer program for generating grounded shielding wires for signal wiring 失效
    用于生成信号线接地屏蔽线的方法和计算机程序

    公开(公告)号：US08516425B2

    公开(公告)日：2013-08-20

    申请号：US13544632

    申请日：2012-07-09

    申请人： Andrey Nikitin ,  Ranko Scepanovic ,  Igor Kucherenko ,  William Lau ,  Cheng-Gang Kong ,  Hui-Yin Seto ,  Andrej Zolotykih ,  Ivan Pavisic ,  Sandeep Bhutani ,  Aiguo Lu ,  Ilya Lyalin

    发明人： Andrey Nikitin ,  Ranko Scepanovic ,  Igor Kucherenko ,  William Lau ,  Cheng-Gang Kong ,  Hui-Yin Seto ,  Andrej Zolotykih ,  Ivan Pavisic ,  Sandeep Bhutani ,  Aiguo Lu ,  Ilya Lyalin

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505 ,  G06F2217/84

    摘要： A system and method are provided for reducing signal skew. The method includes receiving a netlist having components and connections among the components. Each connection has at least one signal wire. A plurality of net groups is identified, each net group including at least some of the connections and for which equivalent routing is desired. For each net group, the method includes systematically routing connection paths between the components for the connections, each connection path extending between an output of one of the components and an input to at least one other of the components and including at least one path fragment. Routing includes, for at least one of the connections of the net group, routing at least one grounded shielding wire in a routing channel adjacent and parallel to at least one of the path fragments of the connection path.

    摘要翻译： 提供了一种减少信号偏移的系统和方法。 该方法包括接收具有组件之间的组件和连接的网表。 每个连接具有至少一个信号线。 识别多个网络组，每个网络组包括至少一些连接并且期望等效路由。 对于每个网络组，所述方法包括系统地路由用于连接的组件之间的连接路径，每个连接路径在组件之一的输出和至少一个其他组件的输入之间延伸并且包括至少一个路径片段。 对于网络组的至少一个连接，路由包括在与连接路径的路径片段中的至少一个相邻并且平行的路由信道中路由至少一个接地屏蔽线。

    Signal delay skew reduction system
    3.
    发明授权
    Signal delay skew reduction system 有权
    信号延迟偏差减少系统

    公开(公告)号：US07996804B2

    公开(公告)日：2011-08-09

    申请号：US12015925

    申请日：2008-01-17

    申请人： Andrey Nikitin ,  Ranko Scepanovic ,  Igor Kucherenko ,  William Lau ,  Cheng-Gang Kong ,  Hui-Yin Seto ,  Andrej Zolotykih ,  Ivan Pavisic ,  Sandeep Bhutani ,  Aiguo Lu ,  Ilya Lyalin

    发明人： Andrey Nikitin ,  Ranko Scepanovic ,  Igor Kucherenko ,  William Lau ,  Cheng-Gang Kong ,  Hui-Yin Seto ,  Andrej Zolotykih ,  Ivan Pavisic ,  Sandeep Bhutani ,  Aiguo Lu ,  Ilya Lyalin

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505 ,  G06F2217/84

    摘要： A system for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist comprising components and connection paths among the components. The method further includes identifying one or more skew-influencing features in a first connection path in the initial netlist that lack corresponding skew-influencing features in a second connection path in the initial netlist. The method also includes generating a skew-corrected netlist wherein the second connection path includes one or more added skew-influencing features corresponding to those of the first connection path. The method further includes outputting the skew-corrected netlist.

    摘要翻译： 根据各种实施例，公开了一种用于减小信号延迟偏差的系统。 本公开的一个说明性实施例涉及一种方法。 根据一个说明性实施例，该方法包括接收包括组件之间的组件和连接路径的初始网表。 该方法还包括识别在初始网表中的第一连接路径中的一个或多个偏斜影响特征，其在初始网表中的第二连接路径中缺少相应的偏斜影响特征。 该方法还包括生成偏差校正网表，其中第二连接路径包括与第一连接路径的相应的一个或多个相加的偏斜影响特征。 该方法还包括输出经偏斜校正的网表。

    SIGNAL DELAY SKEW REDUCTION SYSTEM
    4.
    发明申请
    SIGNAL DELAY SKEW REDUCTION SYSTEM 失效
    信号延迟减少系统

    公开(公告)号：US20110258587A1

    公开(公告)日：2011-10-20

    申请号：US13173855

    申请日：2011-06-30

    申请人： Andrey Nikitin ,  Ranko Scepanovic ,  Igor Kucherenko ,  William Lau ,  Cheng-Gang Kong ,  Hui-Yin Seto ,  Andrej Zolotykh ,  Ivan Pavisic ,  Sandeep Bhutani ,  Aiguo Lu ,  Ilya Lyalin

    发明人： Andrey Nikitin ,  Ranko Scepanovic ,  Igor Kucherenko ,  William Lau ,  Cheng-Gang Kong ,  Hui-Yin Seto ,  Andrej Zolotykh ,  Ivan Pavisic ,  Sandeep Bhutani ,  Aiguo Lu ,  Ilya Lyalin

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505 ,  G06F2217/84

    摘要： A system and method are provided for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist having components and connection paths among the components; identifying a first connection path in the initial netlist that comprises path fragments for which there are no equivalent path fragments in a second connection path in the initial netlist; generating a skew-corrected netlist wherein the second connection path is re-routed to have path fragments equivalent to the path fragments of the first connection path; and outputting the skew-corrected netlist.

    摘要翻译： 根据各种实施例，提供了一种用于减少信号延迟偏差的系统和方法。 本公开的一个说明性实施例涉及一种方法。 根据一个说明性实施例，该方法包括：接收在组件之间具有组件和连接路径的初始网表; 识别所述初始网表中的第一连接路径，其包括在所述初始网表中的第二连接路径中不存在等效路径片段的路径片段; 生成偏差校正网表，其中所述第二连接路径被重新路由以具有等同于所述第一连接路径的路径片段的路径片段; 并输出偏差校正的网表。

    SIGNAL DELAY SKEW REDUCTION SYSTEM
    5.
    发明申请
    SIGNAL DELAY SKEW REDUCTION SYSTEM 有权
    信号延迟减少系统

    公开(公告)号：US20090187873A1

    公开(公告)日：2009-07-23

    申请号：US12015925

    申请日：2008-01-17

    申请人： Andrey Nikitin ,  Ranko Scepanovic ,  Igor Kucherenko ,  William Lau ,  Cheng-Gang Kong ,  Hui-Yin Seto ,  Andrej Zolotykh ,  Ivan Pavisic ,  Sandeep Bhutani ,  Aiguo Lu ,  Ilya Lyalin

    发明人： Andrey Nikitin ,  Ranko Scepanovic ,  Igor Kucherenko ,  William Lau ,  Cheng-Gang Kong ,  Hui-Yin Seto ,  Andrej Zolotykh ,  Ivan Pavisic ,  Sandeep Bhutani ,  Aiguo Lu ,  Ilya Lyalin

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505 ,  G06F2217/84

    摘要： A system for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist comprising components and connection paths among the components. The method further includes identifying one or more skew-influencing features in a first connection path in the initial netlist that lack corresponding skew-influencing features in a second connection path in the initial netlist. The method also includes generating a skew-corrected netlist wherein the second connection path includes one or more added skew-influencing features corresponding to those of the first connection path. The method further includes outputting the skew-corrected netlist.

    摘要翻译： 根据各种实施例，公开了一种用于减小信号延迟偏差的系统。 本公开的一个说明性实施例涉及一种方法。 根据一个说明性实施例，该方法包括接收包括组件之间的组件和连接路径的初始网表。 该方法还包括识别在初始网表中的第一连接路径中的一个或多个偏斜影响特征，其在初始网表中的第二连接路径中缺少对应的偏斜影响特征。 该方法还包括生成偏差校正网表，其中第二连接路径包括与第一连接路径的相应的一个或多个相加的偏斜影响特征。 该方法还包括输出经偏斜校正的网表。

    SIGNAL DELAY SKEW REDUCTION SYSTEM
    6.
    发明申请
    SIGNAL DELAY SKEW REDUCTION SYSTEM 失效
    信号延迟减少系统

    公开(公告)号：US20120278783A1

    公开(公告)日：2012-11-01

    申请号：US13544632

    申请日：2012-07-09

    申请人： Andrey Nikitin ,  Ranko Scepanovic ,  Igor Kucherenko ,  William Lau ,  Cheng-Gang Kong ,  Hui-Yin Seto ,  Andrej Zolotykh ,  Ivan Pavisic ,  Sandeep Bhutani ,  Aiguo Lu ,  Ilya Lyalin

    发明人： Andrey Nikitin ,  Ranko Scepanovic ,  Igor Kucherenko ,  William Lau ,  Cheng-Gang Kong ,  Hui-Yin Seto ,  Andrej Zolotykh ,  Ivan Pavisic ,  Sandeep Bhutani ,  Aiguo Lu ,  Ilya Lyalin

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505 ,  G06F2217/84

    摘要： A system and method are provided for reducing signal skew. The method includes receiving a netlist having components and connections among the components. Each connection has at least one signal wire. A plurality of net groups is identified, each net group including at least some of the connections and for which equivalent routing is desired. For each net group, the method includes systematically routing connection paths between the components for the connections, each connection path extending between an output of one of the components and an input to at least one other of the components and including at least one path fragment. Routing includes, for at least one of the connections of the net group, routing at least one grounded shielding wire in a routing channel adjacent and parallel to at least one of the path fragments of the connection path.

    摘要翻译： 提供了一种减少信号偏移的系统和方法。 该方法包括接收具有组件之间的组件和连接的网表。 每个连接具有至少一个信号线。 识别多个网络组，每个网络组包括至少一些连接并且期望等效路由。 对于每个网络组，所述方法包括系统地路由用于连接的组件之间的连接路径，每个连接路径在组件之一的输出和至少一个其他组件的输入之间延伸并且包括至少一个路径片段。 对于网络组的至少一个连接，路由包括在与连接路径的路径片段中的至少一个相邻并且平行的路由信道中路由至少一个接地屏蔽线。

    Optimizing IC clock structures by minimizing clock uncertainty
    7.
    发明申请
    Optimizing IC clock structures by minimizing clock uncertainty 失效
    通过最小化时钟不确定性优化IC时钟结构

    公开(公告)号：US20060190886A1

    公开(公告)日：2006-08-24

    申请号：US11402146

    申请日：2006-04-11

    申请人： Aiguo Lu ,  Ivan Pavisic ,  Nikola Radovanovic

    发明人： Aiguo Lu ,  Ivan Pavisic ,  Nikola Radovanovic

    IPC分类号： G06F17/50

    CPC分类号： G06F1/10 ,  G01R31/3016

    摘要： A process is provided for optimizing a clock net in the form of a tree having a root defined by a driver pin and a plurality of leaves defined by driven pins. The process includes forcing a first buffer to a center of gravity of the plurality of leaves, inserting a set of second buffers so each leaf is driven by an inserted buffer without timing violations, and moving the first buffer to a center of gravity of the set of second buffers.

    摘要翻译： 提供了一种用于优化具有由驱动器引脚限定的根和由驱动引脚限定的多个叶的树形式的时钟网的过程。 该过程包括将第一缓冲区强制到多个叶片的重心，插入一组第二缓冲器，使得每个叶片被插入的缓冲器驱动而没有定时违反，并且将第一缓冲器移动到该集合的重心 的第二缓冲区。

    Timing recomputation
    8.
    发明授权
    Timing recomputation 有权
    定时重新计算

    公开(公告)号：US06553551B1

    公开(公告)日：2003-04-22

    申请号：US09841825

    申请日：2001-04-25

    申请人： Andrej A. Zolotykh ,  Elyar E. Gasanov ,  Ivan Pavisic ,  Aiguo Lu

    发明人： Andrej A. Zolotykh ,  Elyar E. Gasanov ,  Ivan Pavisic ,  Aiguo Lu

    IPC分类号： G06F1750

    CPC分类号： G06F17/505 ,  G06F17/5031

    摘要： A method of computing timing delays of timing edges of a path of an integrated circuit design. According to the method, all pins within the path are identified, and all timing edges defined by the pins within the path are identified. All pins within the path that are a leading pin of one of the time edge in the path are also identified. For each given pin within the path, a tabulation is made of a number of pins that are upstream from the given pin along a contiguous series of the timing edges in the path. A computational rank is assigned to the given pin based upon the tabulated number for the given pin. The timing edges are ordered for computation based upon the computational rank of the leading pin of each timing edge in the path, to produce an ordered list of timing edges. The timing delays of the timing edges of the path are computed according to the ordered list of timing edges.

    摘要翻译： 一种计算集成电路设计的路径的定时边缘的定时延迟的方法。 根据该方法，识别路径内的所有引脚，并且识别由路径内的引脚限定的所有定时边缘。 路径中的所有引脚都是路径中时间边缘之一的引导引脚。 对于路径内的每个给定的引脚，列出了沿着路径中的连续的时序边缘序列从给定引脚上游的多个引脚。 基于给定引脚的列表号码，给定引脚分配计算等级。 定时边缘根据路径中每个时序边沿的引导引脚的计算等级进行排序，以产生定时边缘的有序列表。 根据定时边缘的有序列表计算路径的定时边缘的定时延迟。

    Method in integrating clock tree synthesis and timing optimization for an integrated circuit design
    9.
    发明授权
    Method in integrating clock tree synthesis and timing optimization for an integrated circuit design 有权
    集成电路设计的时钟树合成和时序优化集成方法

    公开(公告)号：US06550044B1

    公开(公告)日：2003-04-15

    申请号：US09885589

    申请日：2001-06-19

    申请人： Ivan Pavisic ,  Aiguo Lu ,  Andrej A. Zolotykh ,  Elyar E. Gasanov

    发明人： Ivan Pavisic ,  Aiguo Lu ,  Andrej A. Zolotykh ,  Elyar E. Gasanov

    IPC分类号： G06F1750

    CPC分类号： G06F17/5045

    摘要： A method of synthesizing a clock tree for an integrated circuit design is disclosed that includes the steps of constructing an initial balanced clock tree for an integrated circuit design; calculating a clock arrival time for each clock driven cell in the initial clock tree; performing a timing analysis from the clock arrival time calculated for each clock driven cell; and performing a skew optimization concurrently with the timing analysis to correct timing violations discovered by the timing analysis.

    摘要翻译： 公开了一种合成用于集成电路设计的时钟树的方法，其包括以下步骤：为集成电路设计构建初始平衡时钟树; 计算初始时钟树中每个时钟驱动单元的时钟到达时间; 从针对每个时钟驱动单元计算的时钟到达时间执行时序分析; 并且与定时分析同时执行偏斜优化，以校正由定时分析发现的定时违规。

    Optimizing IC clock structures by minimizing clock uncertainty
    10.
    发明申请
    Optimizing IC clock structures by minimizing clock uncertainty 有权
    通过最小化时钟不确定性优化IC时钟结构

    公开(公告)号：US20050010884A1

    公开(公告)日：2005-01-13

    申请号：US10616623

    申请日：2003-07-10

    申请人： Aiguo Lu ,  Ivan Pavisic ,  Nikola Radovanovic

    发明人： Aiguo Lu ,  Ivan Pavisic ,  Nikola Radovanovic

    IPC分类号： G01R31/30 ,  G06F1/10 ,  G06F9/45

    CPC分类号： G06F1/10 ,  G01R31/3016

    摘要： Clock uncertainty between a receiving cell and a launching cell of a net is estimated by back-tracing a first path from the receiving cell toward the clock source and marking each cell having a predetermined character along the first path. A second path from the launching cell toward the clock source is back-traced to a predetermined marked cell. Clock uncertainty is calculated based on the portion of the first path from the predetermined marked cell to the receiving cell. Clock uncertainty is calculated if a slack does not exceed a margin value. In one embodiment, a clock net in the form of a tree is optimized by forcing a first buffer to the center of gravity of a plurality of buffers having nets without timing violations to maximize a common path from the root to the forced buffer and minimize the non-common paths from the forced buffer to the leaves, thereby minimizing clock uncertainty.

    摘要翻译： 通过从接收单元向时钟源的后向跟踪第一路径并且沿着第一路径标记具有预定字符的每个单元来估计接收小区和网络的启动小区之间的时钟不确定性。 从启动单元向时钟源的第二条路径被追溯到预定的标记单元。 基于从预定标记小区到接收小区的第一路径的部分来计算时钟不确定性。 如果松弛不超过余量值，则计算时钟不确定度。 在一个实施例中，通过将第一缓冲器强制为具有网络的多个缓冲器的重心而没有定时违反来最大化从根到强制缓冲器的公共路径，使得最小化 从强制缓冲区到叶片的非公共路径，从而最小化时钟不确定性。