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公开(公告)号:US20050118764A1
公开(公告)日:2005-06-02
申请号:US10724483
申请日:2003-11-28
申请人: Anthony Chou , Michael Chudzik , Toshiharu Furukawa , Oleg Gluschenkov , Paul Kirsch , Byoung Lee , Katsunori Onishi , Heemyoung Park , Kristen Scheer , Akihisa Sekiguchi
发明人: Anthony Chou , Michael Chudzik , Toshiharu Furukawa , Oleg Gluschenkov , Paul Kirsch , Byoung Lee , Katsunori Onishi , Heemyoung Park , Kristen Scheer , Akihisa Sekiguchi
IPC分类号: H01L21/8234 , H01L21/8238 , H01L21/00 , H01L21/3205 , H01L21/336 , H01L21/84
CPC分类号: H01L21/823462 , H01L21/823857
摘要: Gate oxides having different thicknesses are formed on a semiconductor substrate by forming a first gate oxide on the top surface of the substrate, forming a sacrificial hard mask over a selected area of the first gate oxide; and then forming a second gate oxide. A first poly layer may be formed on the first gate oxide, under the hard mask. After the hard mask is removed, a second poly layer may be formed over the second gate oxide and over the first poly layer. This enables the use of high-k dielectric materials, and the first gate oxide can be thinner than the second gate oxide.
摘要翻译: 通过在衬底的顶表面上形成第一栅极氧化物,在半导体衬底上形成具有不同厚度的栅极氧化物,在第一栅极氧化物的选定区域上形成牺牲性硬掩模; 然后形成第二栅极氧化物。 可以在硬掩模下的第一栅极氧化物上形成第一多晶硅层。 在去除硬掩模之后,可以在第二栅极氧化物之上和第一多晶硅层上形成第二多晶硅层。 这使得能够使用高k电介质材料,并且第一栅极氧化物可以比第二栅极氧化物薄。
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公开(公告)号:US07160771B2
公开(公告)日:2007-01-09
申请号:US10724483
申请日:2003-11-28
申请人: Anthony I-Chih Chou , Michael Patrick Chudzik , Toshiharu Furukawa , Oleg Gluschenkov , Paul Daniel Kirsch , Byoung Hun Lee , Katsunori Onishi , Heemyoung Park , Kristen Colleen Scheer , Akihisa Sekiguchi
发明人: Anthony I-Chih Chou , Michael Patrick Chudzik , Toshiharu Furukawa , Oleg Gluschenkov , Paul Daniel Kirsch , Byoung Hun Lee , Katsunori Onishi , Heemyoung Park , Kristen Colleen Scheer , Akihisa Sekiguchi
IPC分类号: H01L21/8242 , H01L21/336 , H01L21/3205
CPC分类号: H01L21/823462 , H01L21/823857
摘要: Gate oxides having different thicknesses are formed on a semiconductor substrate by forming a first gate oxide on the top surface of the substrate, forming a sacrificial hard mask over a selected area of the first gate oxide; and then forming a second gate oxide. A first poly layer may be formed on the first gate oxide, under the hard mask. After the hard mask is removed, a second poly layer may be formed over the second gate oxide and over the first poly layer. This enables the use of high-k dielectric materials, and the first gate oxide can be thinner than the second gate oxide.
摘要翻译: 通过在衬底的顶表面上形成第一栅极氧化物,在半导体衬底上形成具有不同厚度的栅极氧化物,在第一栅极氧化物的选定区域上形成牺牲性硬掩模; 然后形成第二栅极氧化物。 可以在硬掩模下的第一栅极氧化物上形成第一多晶硅层。 在去除硬掩模之后,可以在第二栅极氧化物之上和第一多晶硅层上形成第二多晶硅层。 这使得能够使用高k电介质材料,并且第一栅极氧化物可以比第二栅极氧化物薄。
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公开(公告)号:US20050048732A1
公开(公告)日:2005-03-03
申请号:US10604912
申请日:2003-08-26
申请人: Heemyoung Park , Paul Agnello , Percy Gilbert , Byoung Lee , Patricia O'Neil , Ghavam Shahidi , Jeffrey Welser
发明人: Heemyoung Park , Paul Agnello , Percy Gilbert , Byoung Lee , Patricia O'Neil , Ghavam Shahidi , Jeffrey Welser
IPC分类号: H01L21/336 , H01L21/84 , H01L27/12 , H01L29/423 , H01L29/45 , H01L29/49 , H01L29/786
CPC分类号: H01L29/66772 , H01L21/84 , H01L29/458 , H01L29/6653 , H01L29/6656 , H01L29/66628 , H01L29/78621
摘要: Disclosed is a method and system of forming an integrated circuit transistor having a reduced gate height that forms a laminated structure having a substrate, a gate conductor above the substrate, and at least one sacrificial layer above the gate conductor. The process patterns the laminated structure into at least one gate stack extending from the substrate, forms spacers adjacent to the gate stack, dopes regions of the substrate not protected by the spacers to form source and drain regions adjacent the gate stack, and removes the spacers and the sacrificial layer.
摘要翻译: 公开了一种形成具有降低的栅极高度的集成电路晶体管的方法和系统,其形成具有衬底的层压结构,在衬底上方的栅极导体以及栅极导体上方的至少一个牺牲层。 该过程将层叠结构图案化为从衬底延伸的至少一个栅极堆叠,形成邻近栅极叠层的间隔物,掺杂不被间隔物保护的衬底的区域,以形成邻近栅堆叠的源区和漏区, 和牺牲层。
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