公开(公告)号：US20030176074A1

公开(公告)日：2003-09-18

申请号：US10241653

申请日：2002-09-10

Applicant: Applied Materials, Inc.

Inventor： Alexander Paterson ,  Valentin N. Todorov ,  Jon McChesney ,  Gerhard M. Schneider ,  David Palagashvili ,  John P. Holland ,  Michael S. Barnes

IPC: H01L021/302 ,  H01L021/461

CPC classification number: H01L21/67069 ,  H01J37/32082 ,  H01J37/32458

Abstract: A method and apparatus for processing wafers including a chamber defining a plurality of isolated processing regions. The isolated processing regions have an upper end and a lower end. The chamber further includes a plurality of plasma generation devices each disposed adjacent the upper end of each isolated processing region, and one of a plurality of power supplies connected to each plasma generation device. The output frequency of the plurality of power supplies are phase and/or frequency locked together. Additionally, the chamber includes a plurality of gas distribution assemblies. Each gas distribution assembly is disposed within each isolated processing region. A movable wafer support is disposed within each isolated processing region to support a wafer for plasma processing thereon. The movable wafer support includes a bias electrode coupled to a bias power supply configured to control the bombardment of plasma ions toward the movable wafer support.

Abstract translation: 一种用于处理晶片的方法和装置，包括限定多个隔离处理区域的腔室。 隔离处理区域具有上端和下端。 所述室还包括多个等离子体产生装置，每个等离子体产生装置邻近每个隔离处理区域的上端设置，并且连接到每个等离子体产生装置的多个电源中的一个。 多个电源的输出频率是相位和/或频率锁定在一起的。 另外，腔室包括多个气体分配组件。 每个气体分配组件设置在每个隔离的处理区域内。 可移动的晶片支撑件设置在每个隔离的处理区域内以支撑用于等离子体处理的晶片。 可移动晶片支撑件包括耦合到偏置电源的偏置电极，偏置电源被配置为控制等离子体离子朝向可移动晶片支撑件的轰击。

公开(公告)号：US20030037881A1

公开(公告)日：2003-02-27

申请号：US09931324

申请日：2001-08-16

Applicant: Applied Materials, Inc.

Inventor： Michael S. Barnes ,  John Holland ,  Alexander Paterson ,  Valentin Todorov ,  Farhad Moghadam

IPC: H01L021/302 ,  C23F001/00 ,  C23C016/00

CPC classification number: H01J37/3244 ,  H01J37/32082

Abstract: Apparatus and method for processing a substrate are provided. The apparatus for processing a substrate comprises: a chamber having a first electrode; a substrate support disposed in the chamber and providing a second electrode; a high frequency power source electrically connected to either the first or the second electrode; a low frequency power source electrically connected to either the first or the second electrode; and a variable impedance element connected to one or more of the electrodes. The variable impedance element may be tuned to control a self bias voltage division between the first electrode and the second electrode. Embodiments of the invention substantially reduce erosion of the electrodes, maintain process uniformity, improve precision of the etch process for forming high aspect ratio sub-quarter-micron interconnect features, and provide an increased etch rate which reduces time and costs of production of integrated circuits.

Abstract translation: 提供了用于处理基板的设备和方法。 用于处理衬底的设备包括：具有第一电极的腔室; 设置在所述室中并提供第二电极的衬底支撑件; 电连接到第一或第二电极的高频电源; 电连接到第一或第二电极的低频电源; 以及连接到一个或多个电极的可变阻抗元件。 可调谐可变阻抗元件以控制第一电极和第二电极之间的自偏压分压。 本发明的实施例大大减少电极的侵蚀，保持工艺均匀性，提高用于形成高纵横比亚微米互连特征的蚀刻工艺的精度，并提供增加的蚀刻速率，从而减少集成电路的生产时间和成本 。

公开(公告)号：US20020041160A1

公开(公告)日：2002-04-11

申请号：US10016971

申请日：2001-12-14

Applicant: Applied Materials, Inc.

Inventor： Michael Barnes ,  John Holland ,  Valentin Todorov ,  Mohit Jain ,  Alexander Paterson

IPC: H01J007/24

CPC classification number: H01J37/32174 ,  H01J37/321

Abstract: The present invention generally provides a method for processing a semiconductor substrate, wherein the method includes positioning a substrate in a processing chamber having at least a first and second coils positioned above the substrate and supplying a first electrical current to the first coil. The method further includes supplying a second current to the second coil and regulating a current ratio of electrical current supplied to the first and second coils with a power distribution network in communication with the first and second coils and a single power supply. The method may further include controlling plasma uniformity in a semiconductor processing chamber, wherein the control process includes positioning a first coil above the processing chamber, the first coil being concentrically positioned about a vertical axis of the processing chamber, and positioning a second coil above the processing chamber, the second coil being concentrically positioned about the vertical axis of the processing chamber and radially outward from the first coil. The control process may further include supplying electrical power to the first and second coils with a single power distribution network to selectively regulate a magnetic field intensity generated by the first and second coils above a workpiece in the processing chamber.

Abstract translation: 本发明通常提供一种处理半导体衬底的方法，其中该方法包括将衬底定位在处理室中，该处理室具有位于衬底上方的至少第一和第二线圈，并向第一线圈提供第一电流。 该方法还包括向第二线圈提供第二电流并且通过与第一和第二线圈和单个电源连通的配电网络来调节提供给第一和第二线圈的电流的电流比。 该方法还可以包括控制半导体处理室中的等离子体均匀性，其中控制过程包括将第一线圈定位在处理室上方，第一线圈围绕处理室的垂直轴同心地定位，并且将第二线圈定位在 处理室，第二线圈围绕处理室的垂直轴同心地定位，并且从第一线圈径向向外定位。 控制过程还可以包括用单个配电网络向第一和第二线圈供电，以选择性地调节由处理室中的工件上方的第一和第二线圈产生的磁场强度。