公开(公告)号：US20210134676A1

公开(公告)日：2021-05-06

申请号：US17137099

申请日：2020-12-29

申请人： Applied Materials, Inc.

发明人： Wei-Sheng Lei ,  Brad Eaton ,  Madhava Rao Yalamanchili ,  Saravjeet Singh ,  Ajay Kumar ,  James M. Holden

IPC分类号： H01L21/822 ,  H01L21/308 ,  H01L21/67 ,  H01L21/78 ,  H01J37/32 ,  H01L23/544 ,  B23K26/36 ,  H01L21/3065

摘要： Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.

公开(公告)号：US10163713B2

公开(公告)日：2018-12-25

申请号：US15005700

申请日：2016-01-25

申请人： Applied Materials, Inc.

发明人： Wei-Sheng Lei ,  Brad Eaton ,  Madhava Rao Yalamanchili ,  Saravjeet Singh ,  Ajay Kumar ,  James M. Holden

IPC分类号： H01L21/00 ,  H01L21/822 ,  H01L21/78 ,  H01L21/308 ,  H01J37/32 ,  H01L23/544 ,  B23K26/36 ,  H01L21/3065 ,  H01L21/67 ,  H01L21/683

摘要： Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.

公开(公告)号：US09620379B2

公开(公告)日：2017-04-11

申请号：US14775651

申请日：2014-03-11

申请人： APPLIED MATERIALS, INC.

发明人： Wei-Sheng Lei ,  Mohammad Kamruzzaman Chowdhury ,  Todd Egan ,  Brad Eaton ,  Madhava Rao Yalamanchili ,  Ajay Kumar

IPC分类号： H01L21/67 ,  H01L21/78 ,  H01L21/308 ,  H01L21/3065 ,  B23K26/364 ,  B23K26/40 ,  B23K26/402 ,  H01L21/673 ,  H01L21/687 ,  H01L21/82 ,  B23K103/16 ,  B23K103/00

CPC分类号： H01L21/3086 ,  B23K26/364 ,  B23K26/40 ,  B23K26/402 ,  B23K2103/172 ,  B23K2103/50 ,  B23K2103/56 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/67069 ,  H01L21/67196 ,  H01L21/67207 ,  H01L21/67383 ,  H01L21/68707 ,  H01L21/78 ,  H01L21/82

摘要： Methods of dicing substrates having a plurality of ICs. A method includes forming a multi-layered mask comprising a laser energy absorbing, non-photodefinable topcoat disposed over a water-soluble base layer disposed over the semiconductor substrate. Because the laser light absorbing material layer is non-photodefinable, material costs associated with conventional photo resist formulations may be avoided. The mask is direct-write patterned with a laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the substrate between the ICs. Absorption of the mask layer within the laser emission band (e.g., UV band and/or green band) promotes good scribe line quality. The substrate may then be plasma etched through the gaps in the patterned mask to singulate the IC with the mask protecting the ICs during the plasma etch. The soluble base layer of the mask may then be dissolved subsequent to singulation, facilitating removal of the layer.

公开(公告)号：US08969177B2

公开(公告)日：2015-03-03

申请号：US13917568

申请日：2013-06-13

申请人： Applied Materials, Inc.

发明人： Mohammad Kamruzzaman Chowdhury ,  Wei-Sheng Lei ,  Todd Egan ,  Brad Eaton ,  Madhava Rao Yalamanchili ,  Ajay Kumar

IPC分类号： H01L21/00 ,  H01L21/78 ,  B23K26/36 ,  H01L21/67 ,  B23K26/06 ,  B23K26/18 ,  B23K26/40

CPC分类号： H01L21/67155 ,  B23K26/0624 ,  B23K26/0661 ,  B23K26/18 ,  B23K26/361 ,  B23K26/40 ,  B23K2101/40 ,  B23K2103/172 ,  B23K2103/50 ,  H01L21/67069 ,  H01L21/67115 ,  H01L21/67207 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L2221/68327 ,  H01L2221/68381

摘要： Laser and plasma etch wafer dicing using UV-curable adhesive films. A mask is formed covering ICs formed on the wafer, as well as any bumps providing an interface to the ICs. The semiconductor wafer is coupled to a carrier substrate by a double-sided UV-curable adhesive film. The mask is patterned by laser scribing to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer, below thin film layers from which the ICs are formed. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the ICs. The UV-curable adhesive film is partially cured by UV irradiation through the carrier. The singulated ICs are then detached from the partially cured adhesive film still attached to the carrier substrate, for example individually by a pick and place machine. The UV-curable adhesive film may then be further cured for the film's complete removal from the carrier substrate.

摘要翻译： 激光和等离子体蚀刻晶圆切割使用紫外光固化粘合膜。 形成覆盖在晶片上形成的IC的掩模，以及提供与IC的接口的任何凸块。 半导体晶片通过双面UV固化粘合剂膜耦合到载体基板。 通过激光划线将掩模图案化以提供具有间隙的图案化掩模。 图案化使得半导体晶片的区域在形成IC的薄膜层之下露出。 然后通过图案化掩模中的间隙蚀刻半导体晶片，以对IC进行单片化。 UV固化粘合剂膜通过载体的UV照射部分固化。 然后将分离的IC从仍然附着到载体基底上的部分固化的粘合剂膜分离，例如通过拾取和放置机单独分离。 然后可以进一步固化可UV固化的粘合剂膜，以使膜完全从载体基材上除去。

公开(公告)号：US20200118880A1

公开(公告)日：2020-04-16

申请号：US16706541

申请日：2019-12-06

申请人： Applied Materials, Inc.

发明人： Wei-Sheng Lei ,  Brad Eaton ,  Madhava Rao Yalamanchili ,  Saravjeet Singh ,  Ajay Kumar ,  James M. Holden

IPC分类号： H01L21/822 ,  H01L21/3065 ,  B23K26/36 ,  H01L23/544 ,  H01L21/67 ,  H01J37/32 ,  H01L21/78 ,  H01L21/308

摘要： Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.

公开(公告)号：US10566238B2

公开(公告)日：2020-02-18

申请号：US16193886

申请日：2018-11-16

申请人： Applied Materials, Inc.

发明人： Wei-Sheng Lei ,  Brad Eaton ,  Madhava Rao Yalamanchili ,  Saravjeet Singh ,  Ajay Kumar ,  James M. Holden

IPC分类号： H01L21/00 ,  H01L21/822 ,  H01L21/308 ,  H01L21/67 ,  H01L21/78 ,  H01J37/32 ,  H01L23/544 ,  B23K26/36 ,  H01L21/3065 ,  H01L21/683

摘要： Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.

公开(公告)号：US20190088549A1

公开(公告)日：2019-03-21

申请号：US16193886

申请日：2018-11-16

申请人： Applied Materials, Inc.

发明人： Wei-Sheng Lei ,  Brad Eaton ,  Madhava Rao Yalamanchili ,  Saravjeet Singh ,  Ajay Kumar ,  James M. Holden

IPC分类号： H01L21/822 ,  H01J37/32 ,  H01L21/67 ,  H01L21/3065 ,  B23K26/36 ,  H01L23/544 ,  H01L21/78 ,  H01L21/308 ,  H01L21/683

摘要： Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.

公开(公告)号：US09224625B2

公开(公告)日：2015-12-29

申请号：US13943652

申请日：2013-07-16

申请人： Applied Materials, Inc.

发明人： Wei-Sheng Lei ,  Madhava Rao Yalamanchili ,  Brad Eaton ,  Saravjeet Singh ,  Ajay Kumar

IPC分类号： H01L21/00 ,  H01L21/67 ,  H01L21/78 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/683 ,  B23K26/06 ,  B23K26/36 ,  B23K26/40

CPC分类号： H01L21/67069 ,  B23K26/0624 ,  B23K26/364 ,  B23K26/40 ,  B23K2103/172 ,  B23K2103/50 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/67207 ,  H01L21/6836 ,  H01L21/78 ,  H01L2221/68327

摘要： Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer. The semiconductor wafer is disposed on a water-soluble die attach film. The mask covers and protects the integrated circuits. The mask is patterned with a laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to form singulated integrated circuits. The water-soluble die attach film is then patterned with an aqueous solution.

摘要翻译： 对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。 一种方法包括在半导体晶片上形成掩模。 半导体晶片设置在水溶性芯片附着膜上。 面罩覆盖并保护集成电路。 用激光划线工艺对掩模进行图案化以提供具有间隙的图案化掩模。 图案化使得集成电路之间的半导体晶片的区域露出。 然后通过图案化掩模中的间隙蚀刻半导体晶片，以形成单独的集成电路。 然后用水溶液对水溶性贴片膜进行构图。

公开(公告)号：US09105710B2

公开(公告)日：2015-08-11

申请号：US14091014

申请日：2013-11-26

申请人： APPLIED MATERIALS, INC.

发明人： Wei-Sheng Lei ,  Brad Eaton ,  Aparna Iyer ,  Madhava Rao Yalamanchili ,  Ajay Kumar ,  Jungrae Park

IPC分类号： H01L21/00 ,  H01L21/78 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/67 ,  B23K26/36

CPC分类号： H01L21/78 ,  B23K26/0624 ,  B23K26/364 ,  B23K26/40 ,  B23K2103/172 ,  B23K2103/42 ,  B23K2103/50 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/67069 ,  H01L21/67207

摘要： In embodiments, a hybrid wafer or substrate dicing process involving an initial laser scribe and subsequent plasma etch is implemented for die singulation while also removing an oxidation layer from metal bumps on the wafer. In one embodiment, a method includes forming a mask over the semiconductor wafer covering the plurality of ICs, the plurality of ICs including metal bumps or pads with an oxidation layer. The method includes patterning the mask with a laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the ICs. The method includes plasma etching the semiconductor wafer through the gaps in the patterned mask to singulate the plurality of ICs and remove the oxidation layer from the metal bumps or pads.

摘要翻译： 在实施例中，涉及初始激光划片和随后等离子体蚀刻的混合晶片或衬底切割工艺被实现用于裸片分离，同时还从晶片上的金属凸块去除氧化层。 在一个实施例中，一种方法包括在覆盖多个IC的半导体晶片上形成掩模，所述多个IC包括具有氧化层的金属凸块或焊盘。 该方法包括用激光划线工艺对掩模进行图案化以提供具有间隙的图案化掩模，暴露半导体晶片在IC之间的区域。 该方法包括通过图案化掩模中的间隙对半导体晶片进行等离子体蚀刻，以分离多个IC并从金属凸块或焊盘移除氧化层。

公开(公告)号：US20140179108A1

公开(公告)日：2014-06-26

申请号：US13784591

申请日：2013-03-04

申请人： Applied Materials, Inc.

发明人： Dung Huu Le ,  Graeme Jamieson Scott ,  Jivko Dinev ,  Madhava Rao Yalamanchili ,  Khalid Mohiuddin Sirajuddin ,  Puneet Bajaj ,  Saravjeet Singh

IPC分类号： H01L21/3065 ,  H01L21/67

CPC分类号： H01L21/3065 ,  H01J37/321 ,  H01J37/32623 ,  H01L21/67069

摘要： Embodiments of the invention generally relate to an apparatus and method for plasma etching. In one embodiment, the apparatus includes a process ring with an annular step away from an inner wall of the ring and is disposed on a substrate support in a plasma process chamber. A gap is formed between the process ring and a substrate placed on the substrate support. The annular step has an inside surface having a height ranging from about 3 mm to about 6 mm. During operation, an edge-exclusion gas is introduced to flow through the gap and along the inside surface, so the plasma is blocked from entering the space near the edge of the substrate.

摘要翻译： 本发明的实施例一般涉及用于等离子体蚀刻的装置和方法。 在一个实施例中，该设备包括具有远离环的内壁的环形台阶并且设置在等离子体处理室中的基板支撑件上的处理环。 在工艺环和放置在衬底支架上的衬底之间形成间隙。 环形台阶具有高度范围为约3mm至约6mm的内表面。 在操作期间，引入边缘排除气体流过间隙并沿着内表面，从而阻止等离子体进入基板边缘附近的空间。