公开(公告)号：US08571059B1

公开(公告)日：2013-10-29

申请号：US13194536

申请日：2011-07-29

申请人： Arch Zaliznyak ,  Ramanand Venkata ,  Surinder Singh ,  Henry Y. Lui ,  Tim Tri Hoang ,  Sergey Shumarayev ,  Thungoc M. Tran

发明人： Arch Zaliznyak ,  Ramanand Venkata ,  Surinder Singh ,  Henry Y. Lui ,  Tim Tri Hoang ,  Sergey Shumarayev ,  Thungoc M. Tran

IPC分类号： H04J3/00

CPC分类号： G06F13/385

摘要： Disclosed are apparatus and methods for providing a serial interface with shared datapaths. The apparatus and methods share or re-use components from multiple lower-speed datapaths so as to efficiently provide a higher-speed datapath. In one embodiment, physical coding sublayer circuitry of the lower-speed datapaths is also used by the higher-speed datapath. In another embodiment, physical media access circuitry of the lower-speed data paths is also used by the higher-speed datapath. Other embodiments, aspects and features are also disclosed.

摘要翻译： 公开了用于提供具有共享数据路径的串行接口的装置和方法。 该装置和方法共享或重新使用来自多个低速数据路径的组件，以便有效地提供更高速度的数据通路。 在一个实施例中，低速数据路径的物理编码子层电路也被较高速数据路径使用。 在另一个实施例中，低速数据路径的物理介质访问电路也被高速数据路径使用。 还公开了其它实施例，方面和特征。

公开(公告)号：US08581653B1

公开(公告)日：2013-11-12

申请号：US13328784

申请日：2011-12-16

申请人： Victor Maruri ,  Arch Zaliznyak ,  Ramanand Venkata ,  Henry Y. Lui

发明人： Victor Maruri ,  Arch Zaliznyak ,  Ramanand Venkata ,  Henry Y. Lui

IPC分类号： G06F1/04 ,  H03K3/00

CPC分类号： G06F1/10

摘要： An integrated circuit includes a local clock network that is operable to provide a first clock signal and an interface circuit that is coupled to receive the first clock signal from the local clock network. The interface circuit is operable to generate a second clock signal based on the first clock signal. A clock line is coupled to the interface circuit. The clock line has a fixed length. The second clock signal is provided to a multiplexer circuit through the clock line. The multiplexer circuit provides a third clock signal based on the second clock signal. Another clock network is coupled to receive the third clock signal from the multiplexer circuit.

摘要翻译： 集成电路包括可操作以提供第一时钟信号的本地时钟网络和耦合以从本地时钟网络接收第一时钟信号的接口电路。 接口电路可操作以基于第一时钟信号产生第二时钟信号。 时钟线耦合到接口电路。 时钟线具有固定长度。 第二时钟信号通过时钟线提供给多路复用器电路。 多路复用器电路基于第二时钟信号提供第三时钟信号。 另一个时钟网络被耦合以从多路复用器电路接收第三时钟信号。

公开(公告)号：US07292065B2

公开(公告)日：2007-11-06

申请号：US10910891

申请日：2004-08-03

申请人： Henry Y. Lui ,  Malik Kabani ,  Rakesh Patel ,  Tim Tri Hoang

发明人： Henry Y. Lui ,  Malik Kabani ,  Rakesh Patel ,  Tim Tri Hoang

IPC分类号： H03K19/173

CPC分类号： H03K19/1778 ,  H03K19/17784 ,  H03K19/17792

摘要： Enhanced passgate structures for use in low-voltage systems are presented in which the operational speed of the passgate structures is maximized, while minimizing leakage current when the structure is turned “OFF.” In one arrangement, the VT of the pass-gate structures is increased relative to the VT of other transistors fabricated according to a particular process dimension. In addition, a passgate activation voltage is applied to the passgate structures such that the passgate activation voltage is higher in voltage than a nominal voltage being supplied to circuitry other than the passgate structures.

摘要翻译： 提出了在低压系统中使用的增强型门控结构，其中通道结构的操作速度最大化，同时使结构“OFF”时的漏电流最小化。 在一种布置中，栅极结构的栅极相对于根据特定工艺尺寸制造的其它晶体管的V IN T T T T增加。 此外，通道激活电压被施加到通道结构，使得通电门激活电压的电压高于提供给非门电路结构以外的电路的标称电压。

公开(公告)号：US09515880B1

公开(公告)日：2016-12-06

申请号：US13338898

申请日：2011-12-28

申请人： Ramanand Venkata ,  Henry Y. Lui ,  Victor Maruri ,  David W. Mendel ,  Andrew Bellis

发明人： Ramanand Venkata ,  Henry Y. Lui ,  Victor Maruri ,  David W. Mendel ,  Andrew Bellis

IPC分类号： G06F15/177 ,  G06F1/00 ,  G06F1/04 ,  G06F15/16 ,  H04L12/24 ,  G06F1/10 ,  G06F17/50 ,  G06F9/445

CPC分类号： H04L41/0816 ,  G06F1/04 ,  G06F1/10 ,  G06F9/44505 ,  G06F17/5054 ,  H04J3/0688 ,  H04J3/0691 ,  H04J3/0697 ,  H04L41/0813

摘要： An integrated circuit device may include processing circuits that can be dynamically reconfigured to perform different tasks each of which utilizes different system clock resources. The device may include clock selection circuitry that can selectively route desired clock signals to corresponding processing circuits. The clock signal provided to each processing circuit may be selected based on a current configuration of that processing circuit. Client processing circuits in a network switch may be coupled to interchangeable client networks. The client processing circuits may be dynamically reconfigured based on characteristics of the client networks that are currently coupled to the network switch. By dynamically selecting which clock resources are provided to the processing circuits, clock resources such as global clock signals that are relatively scarce may be reserved for processing circuits that can only function with the relatively scarce clock resources. Arranged in this way, clock resource utilization may be continuously optimized.

摘要翻译： 集成电路设备可以包括可以动态地重新配置以执行不同的任务的处理电路，每个任务利用不同的系统时钟资源。 该装置可以包括时钟选择电路，其可以选择性地将期望的时钟信号路由到相应的处理电路。 可以基于该处理电路的当前配置来选择提供给每个处理电路的时钟信号。 网络交换机中的客户端处理电路可以耦合到可互换的客户端网络。 可以基于当前耦合到网络交换机的客户端网络的特性来动态地重新配置客户端处理电路。 通过动态地选择哪些时钟资源被提供给处理电路，诸如相对稀少的全局时钟信号的时钟资源可以被保留用于只能用相对稀少的时钟资源起作用的处理电路。 以这种方式安排，可以不断优化时钟资源利用。

公开(公告)号：US06970117B1

公开(公告)日：2005-11-29

申请号：US10789406

申请日：2004-02-26

申请人： Henry Y. Lui ,  Chong H. Lee ,  Rakesh Patel ,  Ramanand Venkata ,  John Lam ,  Vinson Chan ,  Malik Kabani

发明人： Henry Y. Lui ,  Chong H. Lee ,  Rakesh Patel ,  Ramanand Venkata ,  John Lam ,  Vinson Chan ,  Malik Kabani

IPC分类号： H03M9/00 ,  H04L7/02

CPC分类号： H04L7/0054 ,  H03M9/00

摘要： A serial data interface for a programmable logic device includes a receiver that deserializes a plurality of channels of received serial data using a recovered clock signal or a phase-aligned received clock signal. Byte boundaries are initially assigned, perhaps arbitrarily, and the deserialized signal is sent to the programmable logic core of the programmable logic device. Programmable logic in the core monitors the byte boundaries on each channel based on the criteria, including any user-defined parameters, programmed into the logic. If a boundary misalignment is detected, a signal is send from the core to bit-slipping circuitry on that channel of the interface to adjust the boundary. The signal could instruct the bit-slipping circuitry to adjust the boundary by the number of bits needed to correct the alignment. Alternatively, the bit-slipping circuitry could operate iteratively, adjusting the boundary by one bit, each cycle, until the signal stops indicating misalignment.

摘要翻译： 用于可编程逻辑器件的串行数据接口包括使用恢复的时钟信号或相位对准的接收时钟信号对接收的串行数据的多个信道反串行的接收器。 字节边界最初可以任意分配，反序列化信号被发送到可编程逻辑器件的可编程逻辑核心。 内核中的可编程逻辑基于标准（包括任何用户定义的参数）来监视每个通道上的字节边界，编程到逻辑中。 如果检测到边界未对准，则在该接口的该通道上将信号从核心发送到位滑动电路以调整边界。 信号可以指示位滑动电路将边界调整校正对准所需的位数。 或者，位打滑电路可以迭代地操作，每个周期将边界调整一个位，直到信号停止指示未对准。

公开(公告)号：US07046174B1

公开(公告)日：2006-05-16

申请号：US11147757

申请日：2005-06-07

申请人： Henry Y. Lui ,  Chong H. Lee ,  Rakesh Patel ,  Ramanand Venkata ,  John Lam ,  Vinson Chan ,  Malik Kabani

发明人： Henry Y. Lui ,  Chong H. Lee ,  Rakesh Patel ,  Ramanand Venkata ,  John Lam ,  Vinson Chan ,  Malik Kabani

IPC分类号： H03M9/00

CPC分类号： H03M9/00 ,  H03K5/135 ,  H04L7/0331

摘要： A serial data interface for a programmable logic device includes a receiver that deserializes a plurality of channels of received serial data using a recovered clock signal or a phase-aligned received clock signal. Byte boundaries are initially assigned, perhaps arbitrarily, and the deserialized signal is sent to the programmable logic core of the programmable logic device. Programmable logic in the core monitors the byte boundaries on each channel based on the criteria, including any user-defined parameters, programmed into the logic. If a boundary misalignment is detected, a signal is send from the core to bit-slipping circuitry on that channel of the interface to adjust the boundary. The signal could instruct the bit-slipping circuitry to adjust the boundary by the number of bits needed to correct the alignment. Alternatively, the bit-slipping circuitry could operate iteratively, adjusting the boundary by one bit, each cycle, until the signal stops indicating misalignment.

摘要翻译： 用于可编程逻辑器件的串行数据接口包括使用恢复的时钟信号或相位对准的接收时钟信号对接收的串行数据的多个信道反串行的接收器。 字节边界最初可以任意分配，反序列化信号被发送到可编程逻辑器件的可编程逻辑核心。 内核中的可编程逻辑基于标准（包括任何用户定义的参数）来监视每个通道上的字节边界，编程到逻辑中。 如果检测到边界未对准，则在该接口的该通道上将信号从核心发送到位滑动电路以调整边界。 信号可以指示位滑动电路将边界调整校正对准所需的位数。 或者，位打滑电路可以迭代地操作，每个周期将边界调整一个位，直到信号停止指示未对准。

公开(公告)号：US06724328B1

公开(公告)日：2004-04-20

申请号：US10454626

申请日：2003-06-03

申请人： Henry Y. Lui ,  Chong H. Lee ,  Rakesh Patel ,  Ramanand Venkata ,  John Lam ,  Vinson Chan ,  Malik Kabani

发明人： Henry Y. Lui ,  Chong H. Lee ,  Rakesh Patel ,  Ramanand Venkata ,  John Lam ,  Vinson Chan ,  Malik Kabani

IPC分类号： H03M900

CPC分类号： H04L7/0054 ,  H03M9/00

摘要： A serial data interface for a programmable logic device includes a receiver that deserializes a plurality of channels of received serial data using a recovered clock signal or a phase-aligned received clock signal. Byte boundaries are initially assigned, perhaps arbitrarily, and the deserialized signal is sent to the programmable logic core of the programmable logic device. Programmable logic in the core monitors the byte boundaries on each channel based on the criteria, including any user-defined parameters, programmed into the logic. If a boundary misalignment is detected, a signal is send from the core to bit-slipping circuitry on that channel of the interface to adjust the boundary. The signal could instruct the bit-slipping circuitry to adjust the boundary by the number of bits needed to correct the alignment. Alternatively, the bit-slipping circuitry could operate iteratively, adjusting the boundary by one bit, each cycle, until the signal stops indicating misalignment.

摘要翻译： 用于可编程逻辑器件的串行数据接口包括使用恢复的时钟信号或相位对准的接收时钟信号对接收的串行数据的多个信道反串行的接收器。 字节边界最初可以任意分配，反序列化信号被发送到可编程逻辑器件的可编程逻辑核心。 内核中的可编程逻辑基于标准（包括任何用户定义的参数）来监视每个通道上的字节边界，编程到逻辑中。 如果检测到边界未对准，则在该接口的该通道上将信号从核心发送到位滑动电路以调整边界。 信号可以指示位滑动电路将边界调整校正对准所需的位数。 或者，位打滑电路可以迭代地操作，每个周期将边界调整一个位，直到信号停止指示未对准。

公开(公告)号：US08812893B1

公开(公告)日：2014-08-19

申请号：US13486482

申请日：2012-06-01

申请人： Ramanand Venkata ,  Henry Y. Lui

发明人： Ramanand Venkata ,  Henry Y. Lui

IPC分类号： G06F1/04 ,  H03K21/00

CPC分类号： H03K21/38 ,  G06F1/10 ,  G06F1/24

摘要： One embodiment relates an apparatus which includes a plurality of local synchronous divider circuits, each local synchronous divider circuit being configured to receive a serial clock signal and a reset signal and generate a local clock signal. The apparatus further includes a clock distribution network configured to distribute the serial clock signal to the plurality of local synchronous divider circuits and a signal distribution network configured to distribute the reset signal to the plurality of local synchronous divider circuits. Another embodiment relates to a method of distributing a serial clock signal and a reset signal to a plurality of local synchronous divider circuits and generating a local clock signal at each of the plurality of local synchronous divider circuits. Other embodiments, aspects, and features are also disclosed.

摘要翻译： 一个实施例涉及一种包括多个本地同步分配器电路的设备，每个本地同步分配器电路被配置为接收串行时钟信号和复位信号并产生本地时钟信号。 该装置还包括时钟分配网络，其被配置为将串行时钟信号分配给多个本地同步分频器电路，以及信号分配网络，配置为将复位信号分配给多个本地同步分频器电路。 另一实施例涉及一种将串行时钟信号和复位信号分配给多个本地同步分频器电路并在多个本地同步分配器电路中的每一个产生本地时钟信号的方法。 还公开了其它实施例，方面和特征。

公开(公告)号：US07570105B1

公开(公告)日：2009-08-04

申请号：US11867416

申请日：2007-10-04

申请人： Sun Woo Baek ,  Henry Y. Lui ,  Surinder Singh

发明人： Sun Woo Baek ,  Henry Y. Lui ,  Surinder Singh

IPC分类号： G05F1/10

CPC分类号： H03L7/0898 ,  H03L7/0814 ,  H03L7/0896

摘要： A charge pump circuit includes switch circuit modules and current modules. The number of switch circuit modules that are coupled to receive current from one of the current modules is variable. The output current of the charge pump circuit increases as more of the switch circuit modules are coupled to receive current from the current modules. The net on-resistance of the switch circuit modules decreases as more of the switch circuit modules are coupled to receive current from the current modules. Charge coupling caused by the net parasitic gate-to-drain capacitance of switching transistors in the switch circuit modules is reduced at smaller output current settings of the charge pump circuit.

摘要翻译： 电荷泵电路包括开关电路模块和电流模块。 耦合以从当前模块之一接收电流的开关电路模块的数量是可变的。 随着更多的开关电路模块被耦合以从当前模块接收电流，电荷泵电路的输出电流增加。 开关电路模块的净导通电阻随着更多的开关电路模块被耦合以从当前模块接收电流而减小。 开关电路模块中的开关晶体管的净寄生栅极到漏极电容引起的电荷耦合在电荷泵电路的较小输出电流设置下被减小。

公开(公告)号：US08739099B1

公开(公告)日：2014-05-27

申请号：US12176379

申请日：2008-07-20

申请人： Victor R. Maruri ,  Boon Jin Ang ,  Henry Y. Lui ,  Surinder Singh ,  Thow Pang Chong ,  Tony K. Ngai

发明人： Victor R. Maruri ,  Boon Jin Ang ,  Henry Y. Lui ,  Surinder Singh ,  Thow Pang Chong ,  Tony K. Ngai

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5031 ,  G06F2217/62

摘要： A method for determining clock uncertainties is provided. The method includes identifying clock transfer types between registers from an integrated circuit design and identifying contributors to the clock uncertainties for each of the clock transfers. The jitter associated with each identified contributor is calculated for both set-up time and hold time. This calculated jitter is incorporated into a slack calculation to determine whether timing constraints are met for a circuit design.

摘要翻译： 提供了一种确定时钟不确定度的方法。 该方法包括从集成电路设计中识别寄存器之间的时钟传输类型，并且识别每个时钟传输的时钟不确定性的贡献者。 针对建立时间和保持时间计算与每个识别的贡献者相关联的抖动。 该计算的抖动被并入到松弛计算中以确定电路设计是否满足时序约束。