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    Apparatus and method for forming a battery in an integrated circuit
    2.
    发明授权
    Apparatus and method for forming a battery in an integrated circuit 失效
    用于在集成电路中形成电池的装置和方法

    公开(公告)号：US06650000B2

    公开(公告)日：2003-11-18

    申请号：US09761123

    申请日：2001-01-16

    申请人： Arne W. Ballantine ,  Robert A. Groves ,  Jennifer L. Lund ,  James S. Nakos ,  Michael B. Rice ,  Anthony K. Stamper

    发明人： Arne W. Ballantine ,  Robert A. Groves ,  Jennifer L. Lund ,  James S. Nakos ,  Michael B. Rice ,  Anthony K. Stamper

    IPC分类号： H01L2900

    CPC分类号： H01M10/052 ,  H01L23/522 ,  H01L23/58 ,  H01L2924/0002 ,  H01M4/5825 ,  H01M6/42 ,  H01M10/0562 ,  H01M10/058 ,  H01M10/425 ,  H01L2924/00

    摘要： A method and structure that provides a battery within an integrated circuit for providing voltage to low-current electronic devices that exist within the integrated circuit. The method includes Front-End-Of-Line (FEOL) processing for generating a layer of electronic devices on a semiconductor wafer, followed by Back-End-Of-Line (BEOL) integration for wires connecting the electronic devices together to form completed electrical circuits of the integrated circuit. The BEOL integration includes forming a multilayered structure of wiring levels on the layer of electronic devices. Each wiring level includes conductive metallization (e.g., metal-plated vias, conductive wiring lines, etc.) embedded in insulative material. The battery is formed during BEOL integration within one or more wiring levels, and the conductive metallization conductively couples positive and negative terminals of the battery to the electronic devices. The battery may have several different topologies relative to the structural and geometrical relationships among the battery electrodes and electrolyte. Multiple batteries may be formed within one or more wiring levels, and may be conductively coupled to the electronic devices. The multiple batteries may be connected in series or in parallel.

    摘要翻译： 在集成电路内提供电池的方法和结构，用于向存在于集成电路内的低电流电子器件提供电压。 该方法包括用于在半导体晶片上产生电子器件层的前端在线（FEOL）处理，随后是用于将电子器件连接在一起的线的后端（BEOL）集成，以形成完整的电 集成电路的电路。 BEOL集成包括在电子设备层上形成布线层的多层结构。 每个布线层包括嵌入在绝缘材料中的导电金属化（例如，金属镀通孔，导电布线等）。 电池在BEOL集成期间在一个或多个布线层次内形成，并且导电金属化将电池的正端子和负极端子电连接到电子设备。 相对于电池电极和电解质之间的结构和几何关系，电池可能具有几种不同的拓扑结构。 多个电池可以形成在一个或多个布线层中，并且可以导电地耦合到电子设备。 多个电池可以串联或并联连接。

    Deep trench decoupling capacitor
    3.
    发明授权
    Deep trench decoupling capacitor 有权
    深沟槽去耦电容

    公开(公告)号：US08492816B2

    公开(公告)日：2013-07-23

    申请号：US12685156

    申请日：2010-01-11

    申请人： James S. Nakos ,  Edmund J. Sprogis ,  Anthony K. Stamper

    发明人： James S. Nakos ,  Edmund J. Sprogis ,  Anthony K. Stamper

    IPC分类号： H01L27/108 ,  H01L29/94

    CPC分类号： H01L28/40 ,  H01L29/66181 ,  H01L29/945

    摘要： Solutions for forming a silicided deep trench decoupling capacitor are disclosed. In one aspect, a semiconductor structure includes a trench capacitor within a silicon substrate, the trench capacitor including: an outer trench extending into the silicon substrate; a dielectric liner layer in contact with the outer trench; a doped polysilicon layer over the dielectric liner layer, the doped polysilicon layer forming an inner trench within the outer trench; and a silicide layer over a portion of the doped polysilicon layer, the silicide layer separating at least a portion of the contact from at least a portion of the doped polysilicon layer; and a contact having a lower surface abutting the trench capacitor, a portion of the lower surface not abutting the silicide layer.

    摘要翻译： 公开了用于形成硅化深沟槽去耦电容器的解决方案。 一方面，半导体结构在硅衬底内包括沟槽电容器，所述沟槽电容器包括：延伸到硅衬底中的外沟槽; 介电衬垫层，与所述外沟槽接触; 所述掺杂多晶硅层在所述外部沟槽内形成内部沟槽; 以及在所述掺杂多晶硅层的一部分上的硅化物层，所述硅化物层将所述接触的至少一部分与所述掺杂多晶硅层的至少一部分分离; 以及具有与所述沟槽电容器邻接的下表面的接触件，所述下表面的一部分不邻接所述硅化物层。

    DEEP TRENCH DECOUPLING CAPACITOR
    4.
    发明申请
    DEEP TRENCH DECOUPLING CAPACITOR 有权
    深层解压电容器

    公开(公告)号：US20110169131A1

    公开(公告)日：2011-07-14

    申请号：US12685156

    申请日：2010-01-11

    申请人： James S. Nakos ,  Edmund J. Sprogis ,  Anthony K. Stamper

    发明人： James S. Nakos ,  Edmund J. Sprogis ,  Anthony K. Stamper

    IPC分类号： H01L29/94 ,  H01L21/02

    CPC分类号： H01L28/40 ,  H01L29/66181 ,  H01L29/945

    摘要： Solutions for forming a silicided deep trench decoupling capacitor are disclosed. In one aspect, a semiconductor structure includes a trench capacitor within a silicon substrate, the trench capacitor including: an outer trench extending into the silicon substrate; a dielectric liner layer in contact with the outer trench; a doped polysilicon layer over the dielectric liner layer, the doped polysilicon layer forming an inner trench within the outer trench; and a silicide layer over a portion of the doped polysilicon layer, the silicide layer separating at least a portion of the contact from at least a portion of the doped polysilicon layer; and a contact having a lower surface abutting the trench capacitor, a portion of the lower surface not abutting the silicide layer.

    摘要翻译： 公开了用于形成硅化深沟槽去耦电容器的解决方案。 一方面，半导体结构在硅衬底内包括沟槽电容器，所述沟槽电容器包括：延伸到硅衬底中的外沟槽; 介电衬垫层，与所述外沟槽接触; 所述掺杂多晶硅层在所述外部沟槽内形成内部沟槽; 以及在所述掺杂多晶硅层的一部分上的硅化物层，所述硅化物层将所述接触的至少一部分与所述掺杂多晶硅层的至少一部分分离; 以及具有与所述沟槽电容器邻接的下表面的接触件，所述下表面的一部分不邻接所述硅化物层。

    Ferro-electric capacitor modules, methods of manufacture and design structures
    7.
    发明授权
    Ferro-electric capacitor modules, methods of manufacture and design structures 有权
    铁电电容器模块，制造方法和设计结构

    公开(公告)号：US08450168B2

    公开(公告)日：2013-05-28

    申请号：US12823728

    申请日：2010-06-25

    申请人： Jeffrey P. Gambino ,  Matthew D. Moon ,  William J. Murphy ,  James S. Nakos ,  Paul W. Pastel ,  Brett A. Philips

    发明人： Jeffrey P. Gambino ,  Matthew D. Moon ,  William J. Murphy ,  James S. Nakos ,  Paul W. Pastel ,  Brett A. Philips

    IPC分类号： H01L21/8238 ,  H01L29/76

    CPC分类号： H01L28/55 ,  H01L27/11507

    摘要： Ferro-electric capacitor modules, methods of manufacture and design structures. The method of manufacturing the ferro-electric capacitor includes forming a barrier layer on an insulator layer of a CMOS structure. The method further includes forming a top plate and a bottom plate over the barrier layer. The method further includes forming a ferro-electric material between the top plate and the bottom plate. The method further includes encapsulating the barrier layer, top plate, bottom plate and ferro-electric material with an encapsulating material. The method further includes forming contacts to the top plate and bottom plate, through the encapsulating material. At least the contact to the top plate and a contact to a diffusion of the CMOS structure are in electrical connection through a common wire.

    摘要翻译： 铁电电容器模块，制造方法和设计结构。 制造铁电电容器的方法包括在CMOS结构的绝缘体层上形成阻挡层。 该方法还包括在阻挡层上形成顶板和底板。 该方法还包括在顶板和底板之间形成铁电材料。 该方法还包括用封装材料封装阻挡层，顶板，底板和铁电材料。 该方法还包括通过封装材料形成与顶板和底板的接触。 至少与顶板的接触和与CMOS结构的扩散的接触通过公共导线电连接。

    Hydrogen barrier liner for ferro-electric random access memory (FRAM) chip
    8.
    发明授权
    Hydrogen barrier liner for ferro-electric random access memory (FRAM) chip 有权
    用于铁电随机存取存储器（FRAM）芯片的阻水衬垫

    公开(公告)号：US08395196B2

    公开(公告)日：2013-03-12

    申请号：US12946915

    申请日：2010-11-16

    申请人： Brian M. Czabaj ,  James V. Hart, III ,  William J. Murphy ,  James S. Nakos

    发明人： Brian M. Czabaj ,  James V. Hart, III ,  William J. Murphy ,  James S. Nakos

    IPC分类号： H01L21/02

    CPC分类号： H01L29/66477 ,  H01L29/6684 ,  H01L29/78391

    摘要： A ferro-electric random access memory (FRAM) chip, including a substrate; a first dielectric layer over the substrate; a gate over the first dielectric layer; a first aluminum oxide layer over the first dielectric layer and the gate; a second dielectric layer over the first aluminum oxide layer; a trench through the second dielectric layer and the first aluminum oxide layer to the gate; a hydrogen barrier liner over the second dielectric layer and lining the trench, and contacting the gate; and a silicon dioxide plug over the hydrogen barrier liner substantially filling the trench.

    摘要翻译： 铁电随机存取存储器（FRAM）芯片，包括衬底; 衬底上的第一电介质层; 第一介电层上的栅极; 在第一介电层和栅极上的第一氧化铝层; 在第一氧化铝层上的第二介电层; 通过第二介电层和第一氧化铝层到沟槽的沟槽; 在所述第二电介质层上方的氢阻挡衬垫，并且衬套所述沟槽，并且与所述栅极接触; 以及基本上填充所述沟槽的氢阻挡衬里上的二氧化硅塞。