公开(公告)号：US07005885B1

公开(公告)日：2006-02-28

申请号：US10370833

申请日：2003-02-21

申请人： Arnold R. Feldman

发明人： Arnold R. Feldman

IPC分类号： H03K19/096

CPC分类号： G06F1/04 ,  G01R31/31726 ,  H03K5/07 ,  H03K5/145 ,  H03K5/151

摘要： A synchronous circuit implements a bypass mode for use in conjunction with an inductive-capacitive (“LC”) buffer. The LC buffer receives differential conventional clock signals, and generates buffered differential conventional clock signals. A synchronous circuit, such as a latch, includes at least two clock receivers. The conventional clock signal is input to the first clock receiver, such as a transistor, and an auxiliary clock is input to a second clock receiver. The conventional clock signal provides timing for the synchronous circuit under a normal mode of operation, and the auxiliary clock signal provides timing for the synchronous circuit under a test mode of operation at a frequency lower than the conventional clock signal.

摘要翻译： 同步电路实现与电感 - 电容（“LC”）缓冲器结合使用的旁路模式。 LC缓冲器接收差分传统时钟信号，并产生缓冲差分传统时钟信号。 诸如锁存器的同步电路包括至少两个时钟接收器。 传统的时钟信号被输入到诸如晶体管的第一时钟接收器，并且辅助时钟被输入到第二时钟接收器。 常规时钟信号在正常操作模式下为同步电路提供定时，并且辅助时钟信号在低于常规时钟信号的频率的测试操作模式下为同步电路提供定时。

公开(公告)号：US06788103B1

公开(公告)日：2004-09-07

申请号：US10213484

申请日：2002-08-06

申请人： Arnold R. Feldman ,  Marc J. Loinaz

发明人： Arnold R. Feldman ,  Marc J. Loinaz

IPC分类号： H03K1716

CPC分类号： H03K3/356139 ,  H03K3/012 ,  H03K19/01707

摘要： A logic circuit employs a shunt peaked technique to enhance the switching speed of the circuit without an increase in power dissipation. A differential logic gate implements a digital circuit function. The shunt peaked logic circuit includes two resistive and two inductive elements. For each differential output line, a resistive element is coupled in series to an inductive element so as to couple the circuit power supply voltage to a differential output line. Under this configuration, the bandwidth of the logic circuit is increased without an increase in power consumption. The logic circuit may be implemented using CML or ECL logic.

摘要翻译： 逻辑电路采用并联峰值技术来增强电路的开关速度，而不增加功耗。 差分逻辑门实现数字电路功能。 分流峰值逻辑电路包括两个电阻和两个电感元件。 对于每个差分输出线，电阻元件串联耦合到电感元件，以将电路电源电压耦合到差分输出线。 在这种配置下，逻辑电路的带宽增加，而不增加功耗。 逻辑电路可以使用CML或ECL逻辑来实现。

公开(公告)号：US07009425B1

公开(公告)日：2006-03-07

申请号：US10778635

申请日：2004-02-13

申请人： Marc J Loinaz ,  Arnold R. Feldman

发明人： Marc J Loinaz ,  Arnold R. Feldman

IPC分类号： H03K17/16

CPC分类号： H03K3/356139 ,  H03K3/012 ,  H03K19/01707

摘要： A logic circuit employs a shunt peaked technique to enhance the switching speed of the circuit without an increase in power dissipation. A differential logic gate implements a digital circuit function. The shunt peaked logic circuit includes two resistive and two inductive elements. For each differential output line, a resistive element is coupled in series to an inductive element so as to couple the circuit power supply voltage to a differential output line. Under this configuration, the bandwidth of the logic circuit is increased without an increase in power consumption. The logic circuit may be implemented using CML or ECL logic. Techniques for improving large signal performance for active shunt-peaked circuits are also disclosed.

摘要翻译： 逻辑电路采用并联峰值技术来增强电路的开关速度，而不增加功耗。 差分逻辑门实现数字电路功能。 分流峰值逻辑电路包括两个电阻和两个电感元件。 对于每个差分输出线，电阻元件串联耦合到电感元件，以将电路电源电压耦合到差分输出线。 在这种配置下，逻辑电路的带宽增加，而不增加功耗。 逻辑电路可以使用CML或ECL逻辑来实现。 还公开了用于提高主动分流峰值电路的大信号性能的技术。

公开(公告)号：US06782249B1

公开(公告)日：2004-08-24

申请号：US09721374

申请日：2000-11-22

申请人： Arnold R. Feldman

发明人： Arnold R. Feldman

IPC分类号： H04B126

CPC分类号： H04B1/30 ,  H03B27/00

摘要： A receiver for direct conversion of RF signals, a particular embodiment comprising a quadrature signal generation circuit having an oscillator with an oscillation frequency of ⅔ times that of the carrier frequency of the RF signal. For the particular embodiment, the quadrature generation circuit includes a divide-by-two division circuit to provide quadrature signals having a frequency of ⅓ that of the carrier frequency, and further including mixers and filters to mix the output of the oscillator and the output of the divide-by-two division circuit so as to provide quadrature signals at the carrier frequency.

摘要翻译： 一种用于RF信号的直接转换的接收机，具体实施例包括具有振荡频率为RF信号的载波频率的振荡频率的2/3倍的振荡器的正交信号产生电路。 对于特定实施例，正交发生电路包括二分频电路以提供频率为载波频率1/3的正交信号，并且还包括混频器和滤波器以将振荡器的输出和 二分频电路的输出，以提供载频的正交信号。

公开(公告)号：US06781445B2

公开(公告)日：2004-08-24

申请号：US09835021

申请日：2001-04-13

申请人： Arnold R. Feldman

发明人： Arnold R. Feldman

IPC分类号： H03F3193

CPC分类号： H03F3/45179 ,  H03F1/226 ,  H03F2200/372 ,  H03F2203/45304 ,  H03F2203/45394 ,  H03F2203/45542 ,  H03F2203/45644 ,  H03F2203/45714

摘要： Methods and apparatus for buffering RF signals. A method includes receiving an input signal, wherein the input signal alternates between a first polarity and a second polarity. From the input signal, a first current is generated, wherein the first current is proportional to the input signal when the input signal has the first polarity, and approximately equal to zero when the input signal has the second polarity, and a second current is generated, wherein the second current is proportional to the input signal when the input signal has the second polarity, and approximately equal to zero when the input signal has the first polarity. A third current is generated proportional to the first current, and a fourth current is generated proportional to the second current. The first and fourth currents are applied to a first terminal of an inductor; and the second and third currents are applied to a second terminal of the inductor.

摘要翻译： 用于缓冲RF信号的方法和装置。 一种方法包括接收输入信号，其中输入信号在第一极性和第二极性之间交替。 从输入信号，产生第一电流，其中当输入信号具有第一极性时，第一电流与输入信号成比例，并且当输入信号具有第二极性时大致等于零，并且产生第二电流 ，其中当输入信号具有第二极性时，第二电流与输入信号成比例，并且当输入信号具有第一极性时，其大致等于零。 与第一电流成比例地产生第三电流，并且与第二电流成比例地产生第四电流。 第一和第四电流被施加到电感器的第一端子; 并且第二和第三电流被施加到电感器的第二端子。