利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

105 条记录 (耗时 0.036 秒)

    Method for reduced electrical fusing time
    4.
    发明授权
    Method for reduced electrical fusing time 失效
    降低电熔时间的方法

    公开(公告)号：US07089136B2

    公开(公告)日：2006-08-08

    申请号：US10604414

    申请日：2003-07-18

    申请人： Darren L. Anand ,  John E. Barth, Jr. ,  Steven F. Oakland ,  Michael R. Ouellette

    发明人： Darren L. Anand ,  John E. Barth, Jr. ,  Steven F. Oakland ,  Michael R. Ouellette

    IPC分类号： G01R31/00

    CPC分类号： G11C17/16 ,  G11C17/18

    摘要： An electrical fuse circuit design for reducing the testing time for a semiconductor device manufactured with redundant eFuse circuitry. A two-to-one multiplexer (MUX) is provided at each eFuse circuit in addition to the fuse latch and pattern latch. Information on which fuse is to be blown is stored in the fuse's pattern latch. The output of the pattern latch is ANDed with a program input to provide a select signal for the MUX. Based on the select signal, the MUX allows the shifted “1” to either go to the next latch in the shift chain or bypass the next latch or latches in the shift chain when the next fuse(s) is not to be blown. Accordingly, the invention enables only those fuse latches associated with fuses that are to be blown to hold up the propagation of the shifted “1” to the next eFuse circuits.

    摘要翻译： 一种电熔丝回路设计，用于减少用冗余eFuse电路制造的半导体器件的测试时间。 除了熔丝锁存器和图案锁存器之外，每个eFuse电路还提供一对二路复用器（MUX）。 保险丝图案锁存器中存储有要熔断保险丝的信息。 模式锁存器的输出与程序输入进行“与”运算以提供MUX的选择信号。 基于选择信号，MUX允许移位的“1”进入移位链中的下一个锁存器，或者在下一个保险丝不被熔断时，旁路下一个锁存器或锁存在换档链中。 因此，本发明仅能够使与熔断器相关联的熔丝锁存器保持被转换的“1”传播到下一个eFuse电路。

    Serial input shift register built-in self test circuit for embedded circuits
    5.
    发明授权
    Serial input shift register built-in self test circuit for embedded circuits 失效
    串行输入移位寄存器内置嵌入式电路自检电路

    公开(公告)号：US5825785A

    公开(公告)日：1998-10-20

    申请号：US653572

    申请日：1996-05-24

    申请人： Robert L. Barry ,  John D. Chickanosky ,  Steven F. Oakland ,  Michael R. Ouellette

    发明人： Robert L. Barry ,  John D. Chickanosky ,  Steven F. Oakland ,  Michael R. Ouellette

    IPC分类号： G01R31/3181 ,  G01R31/3185 ,  G01R31/28

    CPC分类号： G01R31/3185 ,  G01R31/31813 ,  G06F2201/83

    摘要： A highly functional built in self test circuit for embedded compiled macros is useful for testing embedded compiled macros having differing parameters. The built in self test circuit receives a scan vector that describes the parameters of the embedded compiled macro that is to be tested. For, example, the number and width of words stored in a read only memory (ROM) are scanned into the built in self test circuit for controlling the test sequences. A state machine within the built in self test circuit cycles through test vector generation, test vector application, data output scanning and compression for signature analysis. Parallel outputs of the embedded compiled devices are serialized so that regardless of the number of outputs, a serial input shift register can be used for signature generation.

    摘要翻译： 用于嵌入式编译宏的高度内置的自测电路对于测试具有不同参数的嵌入式编译宏非常有用。 内建的自检电路接收一个描述被测试的嵌入式编译宏的参数的扫描向量。 例如，存储在只读存储器（ROM）中的字的数量和宽度被扫描到用于控制测试序列的内置自测试电路中。 内置自检电路中的状态机通过测试向量生成，测试向量应用，数据输出扫描和压缩进行签名分析。 嵌入式编译器件的并行输出被串行化，所以无论输出数量多少，都可以使用串行输入移位寄存器进行签名生成。

    COMPILABLE MEMORY STRUCTURE AND TEST METHODOLOGY FOR BOTH ASIC AND FOUNDRY TEST ENVIRONMENTS
    6.
    发明申请
    COMPILABLE MEMORY STRUCTURE AND TEST METHODOLOGY FOR BOTH ASIC AND FOUNDRY TEST ENVIRONMENTS 审中-公开
    可编程存储器结构和测试方法用于两个ASIC和基准测试环境

    公开(公告)号：US20080256405A1

    公开(公告)日：2008-10-16

    申请号：US12143007

    申请日：2008-06-20

    申请人： Steven M. Eustis ,  James A. Monzel ,  Steven F. Oakland ,  Michael R. Ouellette

    发明人： Steven M. Eustis ,  James A. Monzel ,  Steven F. Oakland ,  Michael R. Ouellette

    IPC分类号： G01R31/3185 ,  G06F11/25 ,  G01R31/3187

    CPC分类号： G11C29/48 ,  G11C29/1201 ,  G11C2029/3202

    摘要： A method of implementing a compilable memory structure configured for supporting multiple test methodologies includes configuring a first plurality of multiplexers for selectively coupling at least one data input path and at least one address path between an external customer connection and a corresponding internal memory connection associated therewith. A second multiplexer is configured for selectively coupling an input of a test latch between a functional memory array connection and a memory logic connection, the memory logic connection coupled to the at least one data input path, with an output of the test latch defining a data out customer connection. Flush logic is configured to direct data from the memory logic connection to the data out customer connection during a test of logic associated with a customer chip, facilitating observation of the memory logic connection at the customer chip.

    摘要翻译： 实现被配置为支持多个测试方法的可编译存储器结构的方法包括配置第一多个多路复用器，用于选择性地耦合至少一个数据输入路径和外部客户连接与与其相关联的对应内部存储器连接之间的至少一个地址路径。 第二多路复用器被配置为选择性地耦合功能存储器阵列连接和存储器逻辑连接之间的测试锁存器的输入，存储器逻辑连接耦合到至少一个数据输入路径，测试锁存器的输出定义数据 客户连接。 冲洗逻辑被配置为在与客户芯片相关联的逻辑的测试期间将数据从存储器逻辑连接引导到数据输出客户连接，以便于观察客户芯片上的存储器逻辑连接。

    Programmable Locking Mechanism For Secure Applications In An Integrated Circuit
    7.
    发明申请
    Programmable Locking Mechanism For Secure Applications In An Integrated Circuit 审中-公开
    可编程锁定机制，用于集成电路中的安全应用

    公开(公告)号：US20080155151A1

    公开(公告)日：2008-06-26

    申请号：US11615137

    申请日：2006-12-22

    申请人： John A. Fifield ,  Steven F. Oakland ,  Michael R. Ouellette

    发明人： John A. Fifield ,  Steven F. Oakland ,  Michael R. Ouellette

    IPC分类号： G06F21/00

    CPC分类号： G06K19/073 ,  G06K19/07309

    摘要： A programmable locking mechanism for use in an integrated circuit is disclosed. In particular, the programmable locking mechanism may include an access code storage circuit for storing a security access code and a code input register whose outputs feed a comparator circuit that generates a locking signal. The state of the locking signal depends on whether the contents of the access code storage circuit and the code input register match. Additionally, a blocking circuit is provided that interrupts a programming input to the access code storage circuit and, thus, allows or denies access via the programming input to the access code storage circuit depending on the state of the locking signal. Additionally, the locking signal is distributed to sensitive logic circuits within the integrated circuit for preventing and/or allowing (depending on state) access thereto.

    摘要翻译： 公开了一种用于集成电路的可编程锁定机构。 特别地，可编程锁定机构可以包括用于存储安全访问代码的访问代码存储电路和其输出馈送产生锁定信号的比较器电路的代码输入寄存器。 锁定信号的状态取决于访问代码存储电路和代码输入寄存器的内容是否匹配。 此外，提供一种阻塞电路，其中断对访问代码存储电路的编程输入，并且因此根据锁定信号的状态允许或拒绝通过对访问代码存储电路的编程输入的访问。 此外，锁定信号被分配到集成电路内的敏感逻辑电路，用于防止和/或允许（取决于状态）对其的访问。

    Method for separating shift and scan paths on scan-only, single port LSSD latches
    8.
    发明授权
    Method for separating shift and scan paths on scan-only, single port LSSD latches 失效
    用于在仅扫描单端口LSSD锁存器上分离移位和扫描路径的方法

    公开(公告)号：US07243279B2

    公开(公告)日：2007-07-10

    申请号：US10604908

    申请日：2003-08-26

    申请人： Darren L. Anand ,  John E. Barth, Jr. ,  Steven F. Oakland ,  Michael R. Ouellette

    发明人： Darren L. Anand ,  John E. Barth, Jr. ,  Steven F. Oakland ,  Michael R. Ouellette

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318536 ,  G01R31/318544

    摘要： A method and circuit design for enabling both shift path and scan path functionality with a single port LSSD latch designed for scan path functionality only, without increasing the device's internal real estate and without substantial increase in overall device real estate. The circuit design eliminates the need for additional logic components to be built into the internal circuitry of the device and also eliminates the cost of providing dual port LSSD latches within the device. Implementation of the invention involves providing a unique configuration of low level logic components as input circuitry that is coupled to a pair of single port LSSD latches that operate as the input latches for the device. The low level logic components accomplishes the splitting of scan chain inputs and shift chain inputs to the input latches and thus enables the single ported LSSD latches to operate with similar functionality as dual ported LSSD latches.

    摘要翻译： 一种方法和电路设计，用于仅使用设计用于扫描路径功能的单端口LSSD锁存器实现移位路径和扫描路径功能，而不会增加设备的内部房地产，而且整体设备的不动产不会大幅增加。 电路设计消除了对设备内部电路内置的其他逻辑元件的需求，并且消除了在器件内提供双端口LSSD锁存器的成本。 本发明的实现涉及提供作为输入电路的低级逻辑组件的独特配置，该输入电路耦合到作为设备的输入锁存器操作的一对单端口LSSD锁存器。 低电平逻辑组件完成扫描链输入和移位链输入到输入锁存器的分割，从而使单端口LSSD锁存器能够与双端口LSSD锁存器类似的功能运行。

    Compilable memory structure and test methodology for both ASIC and foundry test environments
    10.
    发明授权
    Compilable memory structure and test methodology for both ASIC and foundry test environments 有权
    ASIC和代工测试环境的可编程内存结构和测试方法

    公开(公告)号：US07404125B2

    公开(公告)日：2008-07-22

    申请号：US10906147

    申请日：2005-02-04

    申请人： Steven M. Eustis ,  James A. Monzel ,  Steven F. Oakland ,  Michael R. Ouellette

    发明人： Steven M. Eustis ,  James A. Monzel ,  Steven F. Oakland ,  Michael R. Ouellette

    IPC分类号： G01R31/28

    CPC分类号： G11C29/48 ,  G11C29/1201 ,  G11C2029/3202

    摘要： A memory structure configured for supporting multiple test methodologies includes a first plurality of multiplexers configured for selectively coupling at least one data input path and at least one address path between an external customer connection and a corresponding internal memory connection associated therewith. A second multiplexer is configured for selectively coupling an input of a test latch between a functional memory array connection and a memory logic connection coupled to the at least one data input path, with an output of the test latch defining a data out customer connection. Flush logic is further configured to direct data from the memory logic connection to the data out customer connection during a test of logic associated with a customer chip, thereby facilitating observation of the memory logic connection at the customer chip, wherein test elements of the memory structure comprise a scan architecture of a first type, and test elements of the customer chip comprise a scan architecture of a second type.

    摘要翻译： 配置用于支持多种测试方法的存储器结构包括：第一多个复用器，被配置为选择性地耦合至少一个数据输入路径和外部客户连接与与其相关联的对应的内部存储器连接之间的至少一个地址路径。 第二多路复用器被配置用于在功能存储器阵列连接和耦合到所述至少一个数据输入路径的存储器逻辑连接之间选择性地耦合测试锁存器的输入，测试锁存器的输出定义数据输出客户连接。 冲洗逻辑还被配置为在与客户芯片相关联的逻辑的测试期间将数据从存储器逻辑连接引导到数据输出客户连接，从而有助于观察客户芯片处的存储器逻辑连接，其中存储器结构的测试元件 包括第一类型的扫描架构，并且客户芯片的测试元件包括第二类型的扫描架构。